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Recently, the demand for the miniaturization of package substrates has been increasing. Technical innovation has occurred to move package substrate manufacturing steps into CMP applications. Electroplated copper filled trenches on the substrate need to be planarized for multi-level wires of less than $10{\mu}m$. This paper introduces a chemical mechanical planarization (CMP) process as a new package substrate manufacturing step. The purpose of this study is to investigate the effect of surfactant on the dishing and erosion of Cu patterns with the lines and spaces of around $10/10{\mu}m$ used for advanced package substrates. The use of a conventional Cu slurry without surfactant led to problems, including severe erosion of $0.58{\mu}m$ in Cu patterns smaller than $4/6{\mu}m$ and deep dishing of $4.2{\mu}m$ in Cu patterns larger than $14/16{\mu}m$. However, experimental results showed that the friction force during Cu CMP changed to lower value, and that dishing and erosion became smaller simultaneously as the surfactant concentration became higher. Finally, it was possible to realize more globally planarized Cu patterns with erosion ranges of $0.22{\mu}m$ to $0.35{\mu}m$ and dishing ranges of $0.37{\mu}m$ to $0.69{\mu}m$ by using 3 wt% concentration of surfactant.
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참고문헌 (9)
참고문헌 신청
K. Kondo / 2005 / J. Electrochem. Soc 152(11):H173
T. Kobayashi / 2001 / Electrochim. Acta 47:85
K. Takahashi / 2001 / Jpn.J. Appl. Phys 40:3032
C. Andricacos / 1998 / IBM J. Res. Dev 42:567
Seunghyun Ra / 2008 / Micro via and line patterning for PCB using imprint technique / Current Applied Physics 8(6):675~678
T. Kobayashi / 2001 / Electrochim. Acta 47:85
K. Takahashi / 2001 / Jpn.J. Appl. Phys 40:3032
C. Andricacos / 1998 / IBM J. Res. Dev 42:567
Seunghyun Ra / 2008 / Micro via and line patterning for PCB using imprint technique / Current Applied Physics 8(6):675~678
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