지원사업
학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
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연구자들이 자신의 연구와 전문성을 널리 알리고, 새로운 협력의 기회를 만들 수 있는 네트워킹 공간이에요.
논문 기본 정보
- 자료유형
- 학위논문
- 저자정보
- 지도교수
- 류지열
- 발행연도
- 2015
- 저작권
- 부경대학교 논문은 저작권에 의해 보호받습니다.
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초록· 키워드
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Due to the development of integrated circuit technology, many of the features that have been implemented in the analog domain are easily implemented in the digital domain. Although many types of signal processing are moved to the digital domain, the need for analog signal processing in the processing of the natural signal is still important. Therefore, many systems are composed of the ADC(Analog-to-Digital Converter) and DSP(Digital Signal Processor).
This thesis presents the Implementation of a low area SAR(Successive Approximation Register) ADC using MOS(Metal-Insulator-Metal) capacitor. The proposed SAR ADC consists of sample-and-hold stage, capacitor array network stage, comparator stage, SAR control logic stage, digital-to-analog converter(DAC) stage and DAC control logic stage. This SAR ADC is designed to have performance of 12-bit resolution and 1MSps(1 Mega Sampling per second). The proposed circuit is designed using Magnachip/SK Hynix 0.18μm CMOS process, and it is powered by 1.8V supply. Total chip area is reduced by replacing the MOS capacitors instead of the capacitors consisting of overall part in chip area. The proposed circuit in this thesis showed high SNDR(Signal-to-Noise Distortion Ratio) of 70.51dB, and excellent effective bit number of 11.4-bit as compared to conventional research results. The designed circuit also showed low power dissipation of 1.93mW, and small chip area of 0.51mm².
This thesis presents the Implementation of a low area SAR(Successive Approximation Register) ADC using MOS(Metal-Insulator-Metal) capacitor. The proposed SAR ADC consists of sample-and-hold stage, capacitor array network stage, comparator stage, SAR control logic stage, digital-to-analog converter(DAC) stage and DAC control logic stage. This SAR ADC is designed to have performance of 12-bit resolution and 1MSps(1 Mega Sampling per second). The proposed circuit is designed using Magnachip/SK Hynix 0.18μm CMOS process, and it is powered by 1.8V supply. Total chip area is reduced by replacing the MOS capacitors instead of the capacitors consisting of overall part in chip area. The proposed circuit in this thesis showed high SNDR(Signal-to-Noise Distortion Ratio) of 70.51dB, and excellent effective bit number of 11.4-bit as compared to conventional research results. The designed circuit also showed low power dissipation of 1.93mW, and small chip area of 0.51mm².
목차
제1장 서 론제2장 ADC의 구조 및 동작원리2.1 일반적인 ADC의 구조 및 동작원리2.2 주요 성능 지수 및 수식2.3 SAR ADC의 구조 및 동작원리제3장 MOS 커패시터의 구조 및 동작원리제4장 제안하는 MOS 커패시터를 이용한 SAR ADC 설계 및 구현4.1 샘플-앤-홀드단4.2 커패시터 어레이 네트워크단4.3 비교기단4.4 SAR 제어 로직단4.5 DAC 제어 로직단4.6 DAC단4.7 SAR ADC제5장 결과 및 분석5.1 시뮬레이션 결과5.2 성능 분석제6장 결 론
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