지원사업
학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
커뮤니티
연구자들이 자신의 연구와 전문성을 널리 알리고, 새로운 협력의 기회를 만들 수 있는 네트워킹 공간이에요.
이용수
Abstract
Ⅰ. Introduction
Ⅱ. Theory for Experimental Characterization of Interconnects
Ⅲ. Data Analysis of IC Interconnect Parameters
Ⅳ. Signal Delay and Crosstalk Based on Experimental Data
Ⅴ. Conclusion
Acknowledgement
References
저자소개
논문 유사도에 따라 DBpia 가 추천하는 논문입니다. 함께 보면 좋을 연관 논문을 확인해보세요!
Experimental Characterization-Based Signal Integrity Verification of Sub-Micron VLSI Interconnects
Journal of Electrical Engineering and information Science
1997 .10
High-Speed Interconnect Modeling , Simulation and Design
ICVC : International Conference on VLSI and CAD
1993 .01
Parasitic Capacitance Modeling for On-Chip Interconnects
ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications
2003 .07
CAD Models and Verification of Integrated Circuit Interconnects
대한전자공학회 학술대회
1996 .01
CAD Models and Verification of Integrated Circuit Interconnects
대한전자공학회 학술대회
1996 .05
Traveling-wave-based Waveform Approximation Technique (TWA) for Efficient Signal Integrity Verification of Strongly Coupled VLSI Interconnect Lines
대한전자공학회 ISOCC
2007 .10
Time Domain Signal Reflection and Propagation Delay on VLSI Interconnect with Parasite Effect Modeling
KITE JOURNAL OF ELECTRONICS ENGINEERING
1996 .01
Discontinuous RC Interconnect Line Analysis for Accurate Timing Determination
대한전자공학회 ISOCC
2008 .11
An Integrated Environment for Electrical Modeling and Characterization of Packages and Interconnects in High-Speed VLSI System
JOURNAL OF KIEE
1990 .03
Signal Transient and Crosstalk Model of Capacitively and Inductively Coupled VLSI Interconnect Lines
대한전자공학회 ISOCC
2007 .10
A New TWA based Efficient Signal Integrity Verification Technique for Non-Uniform RLC Interconnect Lines
대한전자공학회 학술대회
2005 .05
SIMS: Circuit Interconnect Modeling Environment for VLSI Design
대한전자공학회 학술대회
1994 .07
해석적 시간영역 신호천이 예측 기반 다수 배선 시그널 인테그러티 검증
대한전자공학회 학술대회
2012 .06
Interconnect Line간의 Parasitic Capacitance 계산을 위한 확장 Polynomial
대한전자공학회 학술대회
1994 .01
반도체 회로 연결선의 신뢰도 해석을 위한 전류 해석 기법
전기학회논문지
2010 .08
Time Domain Sensitivity of High-Speed VLSI Interconnects
ICVC : International Conference on VLSI and CAD
1993 .01
Experimental Via Characterization for the Signal Integrity Verification of Discontinuous Interconnect Line
대한전자공학회 ISOCC
2010 .11
SIMS ( SPICE Interconnect Modeling System ) for VLSI design
대한전자공학회 학술대회
1994 .01
Timing Analysis of Discontinuous RC Interconnect Lines
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE
2009 .03
0