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Interconnect characterization on a wafer level was performed. Test patterns for single, two-coupled, and triple-coupled lines were designed by using O.5um CMOS process. Then interconnect capacitances and resistances were experimentally extracted by using two port network measurements. Particularly to eliminate parasitic effects, the Y-parameter de-embedding was performed with specially designed de-embedding patterns. Also, for the purpose of comparisons, capacitance matrices were calculated by using the existing CAD model and field-solver-based commercial simulator, METAL and MEDICI. This work experimentally verifies that existing IC interconnect CAD models or parameter extraction may have large deviation from real values. The signal transient simulation with the experimental data and other methodologies such as field-solver-based simulation and existing models was performed. As expected, they significantly affect on the signal delay and crosstalk. The signal delay due to interconnects dominates the sub-micron-based gate delay (e.g., inverter). particularly, coupling capacitance deviation is so large (about more than 45% in the worst case) that signal integrity cannot be guaranteed with the existing methodologies. The characterization methodologies of this paper can be very usefully employed for the signal integrity verification or the electrical design rule establishments of IC interconnects in the industry.

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Abstract

Ⅰ. Introduction

Ⅱ. Theory for Experimental Characterization of Interconnects

Ⅲ. Data Analysis of IC Interconnect Parameters

Ⅳ. Signal Delay and Crosstalk Based on Experimental Data

Ⅴ. Conclusion

Acknowledgement

References

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UCI(KEPA) : I410-ECN-0101-2009-569-017764780