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논문 기본 정보
- 자료유형
- 학술대회자료
- 저자정보
- 저널정보
- 대한전자공학회 ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications ITC-CSCC : 2009
- 발행연도
- 2009.7
- 수록면
- 294 - 297 (4page)
이용수
초록· 키워드
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This paper proposes an efficient architecture of H.264 sub-pixel interpolation circuit. The circuit based on the proposed architecture does not require any input data buffering and processes the horizontal, vertical and diagonal sub-pixel interpolation operations in parallel. The performance of the circuit is further improved by processing the 1/2-pixel and 1/4-pixel interpolations at the same time. In order to reduce the circuit size, we reuse the internal SRAM’s to store the intermediate data required for parallel processing and do not use any registers. We described the proposed circuit at register trasnfer level. The synthesized circuit using 130㎚ CMOS standard cell library consists of 9,410 gates and has the maximum operating frequency of 584.8㎒. The total number of SPSRAM bits used in our circuit is 3,232.
목차
Abstract
1. Introduction
2. Sub-pixel interpolation algorithm
3. Proposed circuit architecture
4. Experimental results
5. Conclusions
Acknowledgement
References
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UCI(KEPA) : I410-ECN-0101-2012-569-004020396