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논문 기본 정보
- 자료유형
- 학술대회자료
- 저자정보
- 발행연도
- 2008.11
- 수록면
- 292 - 295 (4page)
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초록· 키워드
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The novel low power multitasking bus based on globally asynchronous, locally synchronous system with dynamic voltage and frequency scaling (GALDS) is proposed for System-on-Chips. Our proposed key blocks consists of three distinct components: a novel wrapper-based and bidirectional segmented bus, a newly proposed asynchronous wrapper having bidirectional low-latency FIFOs to communicate between independently clocked synchronous IPs, and a clock distribution system having multiple times of the basic bus clock(fBUS)to be supported for all wrappers and IPs. In addition to being capable of reducing power consumption on multitasking operations, the proposed GALDS has structural merits of the easy scalability and modularity by increasing the bus segments and modifying bit controls, and has a relatively low latency compared with other asynchronous bus systems due to IP communications with multiple times of a basic bus clock. Also, the proposed bus can be supported for ARM-based SOC platform with a wrapper satisfying protocols of AMBA<SUP>™</SUP> AHB between the bus and local IPs. With testing the implementation of the proposed bus, we obtain the robust operations through all dynamically frequency-changed multitasking read and write communications between four master IPs and four slave IPs.
목차
Abstract
Ⅰ. INTRODUCTION
Ⅱ. THE PROPOSED GALDS BUS ARCHITECTURE AND IMPLEMENTATION
Ⅲ. THE GALDS BUS LATENCY MODEL
Ⅳ. SIMULATION RESULT
Ⅴ. CONCLUSION
ACKNOWLEDGMENT
REFERENCES
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UCI(KEPA) : I410-ECN-0101-2013-569-001758842