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논문 기본 정보

자료유형
학술저널
저자정보
Ni Xu (Tsinghua University) Yiyu Shen (Tsinghua University) Sitao Lv (Tsinghua University) Han Liu (Tsinghua University) Woogeun Rhee (Tsinghua University) Zhihua Wang (Tsinghua University)
저널정보
대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE Journal of Semiconductor Technology and Science Vol.16 No.4
발행연도
2016.8
수록면
425 - 435 (11page)

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This paper describes a spread-spectrum clock generation method by utilizing a Δ∑ digital PLL (DPLL) which is solely based on binary phase detection and does not require a linear time-to-digital converter (TDC) or other linear digital-to-time converter (DTC) circuitry. A 1-bit high-order Δ∑ modulator and a hybrid finite-impulse response (FIR) filter are employed to mitigate the phase-folding problem caused by the nonlinearity of the bang-bang phase detector (BBPD). The Δ∑ DPLL employs a two-point modulation technique to further enhance linearity at the turning point of a triangular modulation profile. We also show that the two-point modulation is useful for the BBPLL to improve the spread-spectrum performance by suppressing the frequency deviation at the input of the BBPD, thus reducing the peak phase deviation. Based on the proposed architecture, a 3.2 ㎓ spread-spectrum clock generator (SSCG) is implemented in 65 ㎚ CMOS. Experimental results show that the proposed SSCG achieves peak power reductions of 18.5 ㏈ and 11 ㏈ with 10 ㎑ and 100 ㎑ resolution bandwidths respectively, consuming 6.34 ㎽ from a 1 V supply.

목차

Abstract
Ⅰ. INTRODUCTION
Ⅱ. PHASE-FOLDING REDUCTION IN BBPLL
Ⅲ. SSCG WITH TWO-POINT MODULATION
Ⅳ. CIRCUIT DESIGN
Ⅴ. MEASUREMENT RESULTS
Ⅵ. CONCLUSION
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