지원사업
학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
커뮤니티
연구자들이 자신의 연구와 전문성을 널리 알리고, 새로운 협력의 기회를 만들 수 있는 네트워킹 공간이에요.
논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE Journal of Semiconductor Technology and Science Vol.16 No.4
- 발행연도
- 2016.8
- 수록면
- 425 - 435 (11page)
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초록· 키워드
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This paper describes a spread-spectrum clock generation method by utilizing a Δ∑ digital PLL (DPLL) which is solely based on binary phase detection and does not require a linear time-to-digital converter (TDC) or other linear digital-to-time converter (DTC) circuitry. A 1-bit high-order Δ∑ modulator and a hybrid finite-impulse response (FIR) filter are employed to mitigate the phase-folding problem caused by the nonlinearity of the bang-bang phase detector (BBPD). The Δ∑ DPLL employs a two-point modulation technique to further enhance linearity at the turning point of a triangular modulation profile. We also show that the two-point modulation is useful for the BBPLL to improve the spread-spectrum performance by suppressing the frequency deviation at the input of the BBPD, thus reducing the peak phase deviation. Based on the proposed architecture, a 3.2 ㎓ spread-spectrum clock generator (SSCG) is implemented in 65 ㎚ CMOS. Experimental results show that the proposed SSCG achieves peak power reductions of 18.5 ㏈ and 11 ㏈ with 10 ㎑ and 100 ㎑ resolution bandwidths respectively, consuming 6.34 ㎽ from a 1 V supply.
목차
Abstract
Ⅰ. INTRODUCTION
Ⅱ. PHASE-FOLDING REDUCTION IN BBPLL
Ⅲ. SSCG WITH TWO-POINT MODULATION
Ⅳ. CIRCUIT DESIGN
Ⅴ. MEASUREMENT RESULTS
Ⅵ. CONCLUSION
REFERENCES
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UCI(KEPA) : I410-ECN-0101-2017-569-001108831