지원사업
학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
커뮤니티
연구자들이 자신의 연구와 전문성을 널리 알리고, 새로운 협력의 기회를 만들 수 있는 네트워킹 공간이에요.
논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE Journal of Semiconductor Technology and Science Vol.16 No.5
- 발행연도
- 2016.10
- 수록면
- 595 - 604 (10page)
이용수
초록· 키워드
오류제보하기
Utilizing a standard 130-nm CMOS process, a RF frontend is designed at 24 GHz for automotive collision avoidance radar application. Single IF direct conversion receiver (DCR) architecture is adopted to achieve high integration level and to alleviate the DCR problem. The proposed frontend is composed of a two-stage LNA and downconversion mixers. To save power consumption, and to enhance gain and linearity, stacked NMOS-PMOS g<SUB>m</SUB>-boosting technique is employed in the design of LNA as the first stage. The switch transistors in the mixing stage are biased in subthreshold region to achieve low power consumption. The single balanced mixer is designed in PMOS transistors and is also realized based on the well-known folded architecture to increase voltage headroom. This frontend circuit features enhancement in gain, linearity, and power dissipation. The proposed circuit showed a maximum conversion gain of 19.6 dB and noise figure of 3 dB at the operation frequency. It also showed input and output return losses of less than -10 dB within bandwidth. Furthermore, the port-to-port isolation illustrated excellent characteristic between two ports. This frontend showed the third-order input intercept point (IIP3) of 3 dBm for the whole circuit with power dissipation of 6.5 mW from a 1.5 V supply.
목차
Abstract
I. INTRODUCTION
II. PROPOSED RECEIVER FRONTEND ARCHITECTURE
III. DESIGN AND ANALYSIS OF CMOS CIRCUIT BLOCKS
IV. RESULTS AND CONSIDERATIONS
V. CONCLUSIONS
REFERENCES
참고문헌 (22)
참고문헌 신청
[학술지(정기간행물)] - H. Rastegar / 2015 / A broadband Low Noise Amplifier with built-in linearizer in 0. 13-μm CMOS process / Microelectronics Journal 46 (8) : 698 ~ 705
[학술지(정기간행물)] - Woo-Chang Choi / 2011 / A Programmable Compensation Circuit for System‐on‐Chip Application / JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE 11 (3) : 198 ~ 206
[학술지(정기간행물)] - J. Rudell / 1997 / A 1.9 GHz wide-band IF double conversion MOS receiver for cordless telephone application / IEEE J. Solid-State Circuits 32 (12) : 2071 ~ 2088
[학술지(정기간행물)] - André Mariano / 2014 / Co-design of a wideband double balanced active mixer and transformer-based baluns for 77 GHz radar applications / Microelectron. J.
[학술지(정기간행물)] - Y. Chen / 2008 / A 24-GHz Receiver Frontend With an LO Signal Generator in 0. 18-μm / CMOS, IEEE Trans. on Microw. Theory and Tech. 56 (5) : 1043 ~ 1051
[학술지(정기간행물)] - Woo-Chang Choi / 2011 / A Programmable Compensation Circuit for System‐on‐Chip Application / JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE 11 (3) : 198 ~ 206
[학술지(정기간행물)] - J. Rudell / 1997 / A 1.9 GHz wide-band IF double conversion MOS receiver for cordless telephone application / IEEE J. Solid-State Circuits 32 (12) : 2071 ~ 2088
[학술지(정기간행물)] - André Mariano / 2014 / Co-design of a wideband double balanced active mixer and transformer-based baluns for 77 GHz radar applications / Microelectron. J.
[학술지(정기간행물)] - Y. Chen / 2008 / A 24-GHz Receiver Frontend With an LO Signal Generator in 0. 18-μm / CMOS, IEEE Trans. on Microw. Theory and Tech. 56 (5) : 1043 ~ 1051
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UCI(KEPA) : I410-ECN-0101-2017-569-001646061