지원사업
학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
커뮤니티
연구자들이 자신의 연구와 전문성을 널리 알리고, 새로운 협력의 기회를 만들 수 있는 네트워킹 공간이에요.
논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE Journal of Semiconductor Technology and Science Vol.20 No.2
- 발행연도
- 2020.4
- 수록면
- 187 - 194 (8page)
- DOI
- 10.5573/JSTS.2020.20.2.187
이용수
초록· 키워드
오류제보하기
This paper presents low-power low-noise 24-GHz CMOS LNA (low noise amplifier) for automotive collision avoidance radar. The proposed circuit is fabricated using 65 nm RF CMOS technology, and it is powered by 1.2 V supply. To increase voltage gain and decrease power consumption, this circuit has cascode scheme, and it is optimized to decrease noise figure. Cascode inductive source degeneration technique is also utilized to match the circuit to source impedance. The proposed LNA showed the lowest power consumption of 4.59 mW and the lowest noise figure of 2.98 dB with high voltage gain of 24.3 dB as compared to recently published results. It also showed the smallest chip area of 0.6×0.6 mm², and the size of the core cell of 0.31×0.35 mm² without pads as compared to recently reported results. We expect that the proposed LNA is suitable for GHz-band automotive collision avoidance radar.
목차
Abstract
I. INTRODUCTION
II. CIRCUIT DESIGN AND ANALYSIS
III. RESULTS AND DISCUSSIONS
IV. CONCLUSIONS
REFERENCES
참고문헌 (17)
참고문헌 신청
S.-H. Noh and J.-Y. Ryu, “Linearity Enhancement Technique for GHz-Band LNA,” International Journal of Applied Engineering Research, Vol. 12, No. 19, pp. 9116-9119, October 2017.
H. Rastegar and J.-Y. Ryu, “An Integrated High Linearity CMOS Receiver Frontend for 24-GHz Applications,” Journal of Semiconductor Technology and Science, Vol. 16, No. 5, pp. 595- 604, October 2016.
H. Rastegar and J.-Y. Ryu, “A Broadband Low Noise Amplifier with Built-in Linearizer in 0.13- μm CMOS Process,” Microelectronics Journal, Vol. 46, No. 8, pp. 698-705, August 2015.
W.-H. Chen, G. Liu, B. Zdravko, and A. M. Niknejad, “A Highly Linear Broadband CMOS LNA Employing Noise and Distortion Cancellation,” IEEE Journal of Solid-State Cciruits, Vol. 43, No. 5, pp. 1164-1176. May 2008.
H. Rastegar, J.-H. Lim, and J.-Y. Ryu, “A 2GHz 20dBm IIP3 Low-Power CMOS LNA with Modified DS Linearization Technique,” Journal of Semiconductor Technology and Science, Vol. 16, No. 4, pp. 443-450, August 2016.
H. Rastegar and J.-Y. Ryu, “An Integrated High Linearity CMOS Receiver Frontend for 24-GHz Applications,” Journal of Semiconductor Technology and Science, Vol. 16, No. 5, pp. 595- 604, October 2016.
H. Rastegar and J.-Y. Ryu, “A Broadband Low Noise Amplifier with Built-in Linearizer in 0.13- μm CMOS Process,” Microelectronics Journal, Vol. 46, No. 8, pp. 698-705, August 2015.
W.-H. Chen, G. Liu, B. Zdravko, and A. M. Niknejad, “A Highly Linear Broadband CMOS LNA Employing Noise and Distortion Cancellation,” IEEE Journal of Solid-State Cciruits, Vol. 43, No. 5, pp. 1164-1176. May 2008.
H. Rastegar, J.-H. Lim, and J.-Y. Ryu, “A 2GHz 20dBm IIP3 Low-Power CMOS LNA with Modified DS Linearization Technique,” Journal of Semiconductor Technology and Science, Vol. 16, No. 4, pp. 443-450, August 2016.
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