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논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE Journal of Semiconductor Technology and Science Vol.19 No.1
- 발행연도
- 2019.2
- 수록면
- 42 - 49 (8page)
- DOI
- 10.5573/JSTS.2019.19.1.042
이용수
초록· 키워드
오류제보하기
Being a top-level placement, floorplanning is an important procedure in semiconductor chip design. Optimal floorplanning becomes complicated as the design becomes larger and design constraints become more stringent. In this research, a new effective cell overlap reduction method is developed by using adaptive adjustment of cell density. This is to overcome the weakness of conventional methods which use a single global penalty parameter during analytical placement. Since densely connected cells tend to have large overlaps, the density of the crowded region is intelligently controlled so that the overlap in each region can be effectively reduced. Our floorplanning method uses analytical placement techniques that show good performance in recent benchmark competitions. In experiments using a set of benchmark examples, significantly improved results have been obtained. The pre-legalization overlaps were reduced by more than 90% on the average.
목차
Abstract
Ⅰ. INTRODUCTION
Ⅱ. OVERALL FLOORPLANNING ALGORITHM
Ⅲ. NEW EFFECTIVE ADAPTIVE DENSITY CONTROL FOR OVERLAP REDUCTION
Ⅳ. EXPERIMENTAL RESULTS
Ⅴ. CONCLUSIONS
REFERENCES
참고문헌 (8)
참고문헌 신청
J. Lin, P. Chiu and Y. Chang, SAINT: Handling Module Folding and Alignment in Fixed-outline Floorplans for 3D ICs, Proc. ICCAD, pp. 1-7, 2016.
J. Lin and J. Yang, Routability-driven TSV-aware Floorplanning Methodology for Fixed-outline 3D ICs, IEEE Trans. Comput.-Aided Design Circuits Syst., Vol. 36, No. 11, pp. 1856-1868, Nov. 2017.
S. N. Adya and I. L. Markov, Fixed-outline floorplanning: enabling hierarchical design, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., Vol. 11, No. 6, pp. 1120-1135, Dec. 2003.
S. Nakatake et al., Module packing based on the BSG-structure and IC layout applications, IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., Vol. 17, No. 6, pp. 519-530, Jun. 1998.
T. Chan et al., “mPL6: Enhanced multilevel mixedsize placement,” Proc. ACM ISPD, pp. 212?214, 2006.
J. Lin and J. Yang, Routability-driven TSV-aware Floorplanning Methodology for Fixed-outline 3D ICs, IEEE Trans. Comput.-Aided Design Circuits Syst., Vol. 36, No. 11, pp. 1856-1868, Nov. 2017.
S. N. Adya and I. L. Markov, Fixed-outline floorplanning: enabling hierarchical design, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., Vol. 11, No. 6, pp. 1120-1135, Dec. 2003.
S. Nakatake et al., Module packing based on the BSG-structure and IC layout applications, IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., Vol. 17, No. 6, pp. 519-530, Jun. 1998.
T. Chan et al., “mPL6: Enhanced multilevel mixedsize placement,” Proc. ACM ISPD, pp. 212?214, 2006.
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