지원사업
학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
커뮤니티
연구자들이 자신의 연구와 전문성을 널리 알리고, 새로운 협력의 기회를 만들 수 있는 네트워킹 공간이에요.
논문 기본 정보
- 자료유형
- 학술대회자료
- 저자정보
- 발행연도
- 2019.11
- 수록면
- 30 - 33 (4page)
이용수
초록· 키워드
오류제보하기
Phase locked loops (PLLs) are essential circuits to generate stable clocks in many applications requiring low noise and jitter, such as wireless communications and analog-to-digital converters. Among the various PLL structures, the sub-sampling fractional-N PLL structure utilizing a digital-to-time converter (DTC) is the most effective one to achieve improved in-band noise. However, this structure requires a high resolution DTC for noise protection, which exposes obvious limitations in terms of design complexity and difficulty, and power consumption. To tackle the limitations of the existing structure, this paper proposes new 2.4 GHz sub-sampling fractional-N PLL based on a hybrid phase interpolator (PI) composed of capacitors and tournaments. The introduction of the PI greatly reduces DTC overhead, while achieving low power consumption through a capacitor structure interpolator, and assuring the high accuracy of the phase generation through the tournament interpolator. The proposed PLL is designed in 65nm CMOS technology and demonstrates that the fabricated chip achieves 162 fs rms jitter, -247.3 dB FoM and -47 dBc fractional spurs.
목차
Abstract
I. 서론
II. 기존 서브-샘플링 위상 고정루프
Ⅲ. 하이브리드 위상 보간기를 이용한 서브-샘플링 위상 고정 루프
Ⅳ. 결론 및 향후 연구 방향
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