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학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
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논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE Journal of Semiconductor Technology and Science Vol.23 No.3
- 발행연도
- 2023.6
- 수록면
- 202 - 205 (4page)
- DOI
- 10.5573/JSTS.2023.23.3.202
이용수
초록· 키워드
오류제보하기
This paper presents the implementation of a Resolution-Multiplied Time-to-Digital Converter (RM-TDC) and a Sub-harmonically Injection locked Phase-Locked Loop (SIPLL) based on a digital frequency loop to correct frequency offset. The proposed design performs frequency adjustment via a Sampled-Edge-Direction-Dependent Frequency Detector (SEDD-FD), achieving faster and more efficient frequency lock. Also, RM-TDC was used to detect the frequency offset in order to enhance jitter performance. This design has an integrated jitter of 676 fs, a phase noise of -114.26 dBc/Hz at 10 Mhz, occupies an area of 0.052 mm², and consumes 2.43 mW. It is manufactured using a 65 nm CMOS process.
목차
Abstract
I. INTRODUCTION
II. ARCHITECTURE
III. CIRCUIT DESCRIPTION
IV. MEASUREMENT RESULTS
V. CONCLUSIONS
REFERENCES
참고문헌 (5)
참고문헌 신청
Lin, C.-Y., Hung, Y.-T., & Lin, T.-H, “A 2.4-GHz 500-uW 370-fsrms Integrated Jitter Sub-Sampling Sub-Harmonically Injection-Locked PLL in 90-nm CMOS,” in IEEE Asian Solid-State Circuit Conf. (ASSCC), pp. 91-94, Nov. 2019.
Jin, Xuefan, et al, “A 4-GHz Sub-hamonically Injection-Locked Phase-Locked Loop with Self-Calibrated Injectioin Timing and Pulsewidth,” in IEEE Asian Solid-State Circuit Conf. (ASSCC), pp. 83-96, Nov. 2019.
Y.-H. Tseng, C.-W. Yeh, and S.-I. Liu, “A 2.25-2.7 GHz Area-Efficient Subharmonically Injection-Locked Fractional-N Frequency Synthesizer With a Fast-Converging Correlation Loop,” IEEE Trans. Circuits Syst. Ⅰ, Reg. Papers, vol. 64, no. 4, pp. 811-822, Apr
Zhang, Zhao, et al, “A 18-to-23 GHz -253.5dBFoM Sub-Harmonically Injection-Locked ADPLL with ILFD Aided Adaptvie Injection Timing Alignment Technique,” in IEEE Asian Solid-State Circuit Conf. (ASSCC), pp. 249-252, Nov. 2017.
M.-S. Choo, et al, “A PVT Variation-Robust All-Digital Injection-Locked Clock Multiplier With Real-Time Offset Tracking Using Time-Division Dual Calibration,” IEEE J. Solid-State Circuits, vol. 56, no. 8, pp. 2525-2538, Aug. 2021.
Jin, Xuefan, et al, “A 4-GHz Sub-hamonically Injection-Locked Phase-Locked Loop with Self-Calibrated Injectioin Timing and Pulsewidth,” in IEEE Asian Solid-State Circuit Conf. (ASSCC), pp. 83-96, Nov. 2019.
Y.-H. Tseng, C.-W. Yeh, and S.-I. Liu, “A 2.25-2.7 GHz Area-Efficient Subharmonically Injection-Locked Fractional-N Frequency Synthesizer With a Fast-Converging Correlation Loop,” IEEE Trans. Circuits Syst. Ⅰ, Reg. Papers, vol. 64, no. 4, pp. 811-822, Apr
Zhang, Zhao, et al, “A 18-to-23 GHz -253.5dBFoM Sub-Harmonically Injection-Locked ADPLL with ILFD Aided Adaptvie Injection Timing Alignment Technique,” in IEEE Asian Solid-State Circuit Conf. (ASSCC), pp. 249-252, Nov. 2017.
M.-S. Choo, et al, “A PVT Variation-Robust All-Digital Injection-Locked Clock Multiplier With Real-Time Offset Tracking Using Time-Division Dual Calibration,” IEEE J. Solid-State Circuits, vol. 56, no. 8, pp. 2525-2538, Aug. 2021.
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