지원사업
학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
커뮤니티
연구자들이 자신의 연구와 전문성을 널리 알리고, 새로운 협력의 기회를 만들 수 있는 네트워킹 공간이에요.
논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE Journal of Semiconductor Technology and Science Vol.16 No.6
- 발행연도
- 2016.12
- 수록면
- 860 - 866 (7page)
이용수
초록· 키워드
오류제보하기
An injection-locked ring phase-locked loop (ILRPLL) using a charge-stored complementary switch (CSCS) injection technique is described in this paper. The ILRPLL exhibits a wider lock range compared to other conventional ILRPLLs, owing to the improvement of the injection effect by the proposed CSCS. A frequency calibration loop and a device mismatch calibration loop force the frequency error to be zero to minimize jitter and reference spur. The prototype chip fabricated in 65-nm CMOS technology achieves a 285-fs<SUB>rms</SUB> integrated jitter at 3.328 GHz from the reference clock of 52 MHz while consuming 7.16 mW. The figure-of-merit of the ILRPLL is ‒242.4 dB.
목차
Abstract
Ⅰ. INTRODUCTION
Ⅱ. ARCHITECTURE
Ⅲ. EXPERIMENTAL RESULTS
Ⅴ. CONCLUSIONS
REFERENCES
참고문헌 (8)
참고문헌 신청
A. Musa / 2014 / A compact, lowpower and low-jitter dual-loop injection locked PLL using all-digital PVT calibration / IEEE Journal of Solid-State Circuits 49(1):50~60
B. M. Helal / 2009 / A low jitter programmable clock multiplier based on a pulse injection-locked oscillator with a highly-digital tuning loop / IEEE Journal of Solid-State Circuits 44(5):1391~1400
S. Choi / 2016 / A 185-fsrmsintegrated-jitter and ‒ 245dB FOM PVT-robust ring-VCO-based injection-locked clock multiplier with a continuous frequency-tracking loop using a replica-delay cell and a dual-edge phase detector / 2016 IEEE International Solid-State Circuits Conference (ISSCC) :194~195
J. Lee / 2009 / Study of subharmonically injection-locked PLLs / IEEE Journal of Solid-State Circuits 44(5):1539~1553
A. Elkholy / 2015 / Design and analysis of lowpower high-frequency robust sub-harmonic injection-locked clock multipliers / IEEE Journal of Solid-State Circuits 50(12):3160~3174
B. M. Helal / 2009 / A low jitter programmable clock multiplier based on a pulse injection-locked oscillator with a highly-digital tuning loop / IEEE Journal of Solid-State Circuits 44(5):1391~1400
S. Choi / 2016 / A 185-fsrmsintegrated-jitter and ‒ 245dB FOM PVT-robust ring-VCO-based injection-locked clock multiplier with a continuous frequency-tracking loop using a replica-delay cell and a dual-edge phase detector / 2016 IEEE International Solid-State Circuits Conference (ISSCC) :194~195
J. Lee / 2009 / Study of subharmonically injection-locked PLLs / IEEE Journal of Solid-State Circuits 44(5):1539~1553
A. Elkholy / 2015 / Design and analysis of lowpower high-frequency robust sub-harmonic injection-locked clock multipliers / IEEE Journal of Solid-State Circuits 50(12):3160~3174
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UCI(KEPA) : I410-ECN-0101-2017-569-001935129