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논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE Journal of Semiconductor Technology and Science Vol.10 No.3
- 발행연도
- 2010.9
- 수록면
- 240 - 250 (11page)
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초록· 키워드
오류제보하기
Double Gate MOSFETs (DG MOSFETs) with doping in one or two thin layers of an o therwise intrinsic channel are simulated to obtain the transport characteristics, threshold voltage and leakage current. Two different device structures- one with doping on two layers near the top and bottom oxide layers and another with doping on a single layer at the centre- are simulated and the variation of device parameters with a change in doping concentration and doping layer thickness is studied. It is observed that an n-doped layer in the channel reduces the threshold voltage and increases the drive current, when compared with a device of undoped channel. The reduction in the threshold voltage and increase in the drain current are found to increase with the thickness and the level of doping of the layer. The leakage current is larger than that of an undoped channel, but less than that of a uniformly doped channel. For a channel with p-doped layer, the threshold voltage increases with the level of doping and the thickness of the layer, accompanied with a reduction in drain current. The devices with doped middle layers and doped gate layers show almost identical behavior, apart from the slight difference in the drive current. The doping level and the thickness of the layers can be used as a tool to adjust the threshold voltage of the device indicating the possibility of easy fabrication of ICs having FETs of different threshold voltages, and the rest of the channel, being intrinsic having high mobility, serves to maintain high drive current in comparison with a fully doped channel.
목차
Abstract
Ⅰ. INTRODUCTION
Ⅱ. DEVICE STRUCTURE AND SIMULATION SCHEME OF LAYER-DOPED DG MOSFET
Ⅲ. EFFECT OF LAYER DOPING THE DG MOSFET CHANNEL
Ⅳ. CONCLUSIONS
REFERENCES
참고문헌 (39)
참고문헌 신청
1. [학술지(정기간행물)] - K. Suzuki / 1993 / Scaling theory for Double-Gate SOI MOSFETs / IEEE Trans. Electron Devices 40 (12) : 2326 ~ 2329
2. [학술지(정기간행물)] - R.W.Keyes / 1975 / The effect of randomness in the distribution of impurity atoms on FET thresholds / Appl. Phys. A 8 (3) : 251 ~ 259
3. [학술지(정기간행물)] - R.W.Keyes / 1975 / Effect of randomness in the distribution of impurity ions on FET thresholds in integrated electronics / IEEE J. Solid-State Circuits 10 (4) : 245 ~ 247
4. [학술지(정기간행물)] - A.Asenov / 1998 / Random dopant induced threshold voltage lowering and fluctuations in Sub-0.1μm MOSFETs: A 3-D atomistic simulation study / IEEE Trans. Electron Devices 45 : 2505 ~ 2513
5. [학술지(정기간행물)] - A.Asenov / 1999 / Random dopant induced threshold voltage lowering and fluctuations in sub 50 nm MOSFETs: a statistical 3D ‘atomistic’ simulation study / Nanotechnology 10 : 153 ~ 158
2. [학술지(정기간행물)] - R.W.Keyes / 1975 / The effect of randomness in the distribution of impurity atoms on FET thresholds / Appl. Phys. A 8 (3) : 251 ~ 259
3. [학술지(정기간행물)] - R.W.Keyes / 1975 / Effect of randomness in the distribution of impurity ions on FET thresholds in integrated electronics / IEEE J. Solid-State Circuits 10 (4) : 245 ~ 247
4. [학술지(정기간행물)] - A.Asenov / 1998 / Random dopant induced threshold voltage lowering and fluctuations in Sub-0.1μm MOSFETs: A 3-D atomistic simulation study / IEEE Trans. Electron Devices 45 : 2505 ~ 2513
5. [학술지(정기간행물)] - A.Asenov / 1999 / Random dopant induced threshold voltage lowering and fluctuations in sub 50 nm MOSFETs: a statistical 3D ‘atomistic’ simulation study / Nanotechnology 10 : 153 ~ 158
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