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논문 기본 정보
- 자료유형
- 학술대회자료
- 저자정보
- 발행연도
- 2008.11
- 수록면
- 36 - 39 (4page)
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초록· 키워드
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Leakage power has become a major concern in mobile device and power gating is a very popular technique to reduce the leakage power. In this paper, we discuss two important optimization issues in power gating designs. One is the sizing problem of the sleep transistors which are the trade-off between the size and IR drop noise in the power gating designs. We also discuss the wake-up schedule optimization and propose efficient wake-up schedule for a power gating design. Our experimental results are very encouraging.
목차
ABSTRACT
Ⅰ. INTRODUCTION
Ⅱ. POWER GATING DESIGN FLOW
Ⅲ. SLEEP TRANSISTOR SIZING PROBLEM
Ⅳ. WAKE-UP SCHEDULE FOR WAKE-UP TIME MINIMIZATION
Ⅴ. EXPERIMENTAL RESULTS
Ⅵ. CONCLUSIONS
REFERENCES
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UCI(KEPA) : I410-ECN-0101-2013-569-001758251