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논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE Journal of Semiconductor Technology and Science Vol.9 No.4
- 발행연도
- 2009.12
- 수록면
- 240 - 248 (9page)
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초록· 키워드
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Moore’s law has driven silicon technology scale down aggressively, and it results in significant increase of leakage current on nano-meter scale CMOS. Especially, in mobile devices, leakage current has been one of designers’ main concerns, and thus many studies have introduced low power methodologies. However, there are few studies to minimize implementation cost in the mixed use of the methodologies to the best of our knowledge. In this paper, we introduce industrial applications of low power design methodologies for the decrease of leakage current. We focus on the design cost reduction of power gating and reverse body bias when used together. Also, we present voltage scale as an alternative to reverse body bias. To sustain gate leakage current, we discuss the adoption of high-κ metal gate, which cuts gate leakage current by a factor of 10 in 32 ㎚ CMOS technology. A 45 ㎚ mobile SoC is shown as the case study of the mixed use of low power methodologies.
목차
Abstract
Ⅰ. INTRODUCTION
Ⅱ. POWER GATING
Ⅲ. REVERSE BODY BIASING
Ⅳ. ADAPTIVE VOLTAGE SCALING
Ⅴ. HIGH-k METAL GATE
Ⅵ. CASE STUDY: LEAKAGE REDUCTION IN 45 NM COMMERCIAL MOBILE SOC
Ⅶ. CONCLUSIONS
REFERENCES
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