지원사업
학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
커뮤니티
연구자들이 자신의 연구와 전문성을 널리 알리고, 새로운 협력의 기회를 만들 수 있는 네트워킹 공간이에요.
논문 기본 정보
- 자료유형
- 학술대회자료
- 저자정보
- 저널정보
- 대한전자공학회 ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications ITC-CSCC : 2008
- 발행연도
- 2008.7
- 수록면
- 205 - 208 (4page)
이용수
초록· 키워드
오류제보하기
On cutting-edge semiconductor process, leakage current varies drastically due to process variation and temperature changes. At the circuit design stage, it is difficult to estimate the amount of leakage current at every manufactured chip. Therefore an on-chip function of measuring leakage current is required. The Virtual-ground (VGND) voltage of MTCMOS circuits increases during the sleep operation, because parasitic capacitance of a VGND line is charged up by the leakage current. By applying this behavior, we design leakage monitor circuits using ASPLA 90nm technology. Simulation results show that monitor delay-time is 165ns and monitor-error is 6% under the typical process condition, 25℃ and operating frequency of 200㎒. Power dissipation of designed circuits is 29㎼ in the monitoring mode and 15㎼ in the standby mode.
목차
Abstract
1. Introduction
2. Scheme for leakage measurement
3. Leakage monitor circuit
4. Circuit analysis
5. Conclusion and future work
6. Acknowledgement
References
참고문헌 (0)
참고문헌 신청함께 읽어보면 좋을 논문
논문 유사도에 따라 DBpia 가 추천하는 논문입니다. 함께 보면 좋을 연관 논문을 확인해보세요!
-
MTCMOS Post-Mask Performance Enhancement
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE
2004 .12
-
고성능 저전력 모바일 컴퓨팅 제품을 위한 MTCMOS ASIC 설계 방식
전자공학회논문지-SD
2005 .02
-
Power-Switch Clustering Method for Static Timing Analysis
ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications
2008 .07
-
Analysis on MTCMOS Circuit based on Lumped RC Model for Virtual Ground Line
대한전자공학회 ISOCC
2005 .10
-
How Forward Body Bias Helps to Reduce Ground Bouncing Noise and Silicon Area in MTCMOS Circuits : Divulging the Basic Mechanism
대한전자공학회 ISOCC
2010 .11
-
0.5V동작 MTCMOS / SIMOX회로 ( A 0.5 V MTCMOS / SIMOX Circuit with 200 ps Logic Gate )
대한전자공학회 워크샵
1996 .01
-
MTCMOS Post-Mask Performance Enhancement
대한전자공학회 ISOCC
2004 .10
-
Optimum Supply Voltage and Sleep Transistor Sizing for Energy Minimization in Latency-Constrained MTCMOS Circuits
대한전자공학회 ISOCC
2006 .10
-
Sleep Transistor Forward Body Bias : an Extra Knob to Lower Ground Bouncing Noise in MTCMOS Circuits
대한전자공학회 ISOCC
2009 .11
-
Clock-free MTCMOS Flip-flops with High Speed and Low Power
ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications
2004 .07
-
Standby Mode에서 Control Transistor 삽입을 이용한 CMOS Logic Circuits의 Leakage 감소기술
대한전자공학회 학술대회
2006 .11
-
극저 누설전류를 가지는 1.2V 모바일 DRAM
대한전자공학회 학술대회
2007 .07
-
극저 누설전류를 가지는 1.2V 모바일 DRAM
대한전자공학회 학술대회
2007 .07
-
A Novel Leakage Power Reduction Technique for CMOS Circuit Design
대한전자공학회 ISOCC
2010 .11
-
Multi-Phase Sleep Signal Modulation for Mode Transition Noise Mitigation in MTCMOS Circuits
대한전자공학회 ISOCC
2012 .11
-
SOC Power Off – Power Noise Analysis
대한전자공학회 ISOCC
2009 .11
-
누전차단기가 설치된 옥내전로에서의 화재위험성
한국안전학회 학술발표회
1998 .01
-
Effectiveness of Power Gating for a Superscalar processor
ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications
2009 .07
-
Improvement to the Leakage Power Minimization Techniques for Arithmetic Circuits
대한전자공학회 ISOCC
2005 .10
-
An Enhancement of Circuit Simulation by a New Circuit Reduction Method
ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications
1997 .01
이 논문의 저자 정보
이 논문과 함께 이용한 논문
최근 본 자료
댓글(0)
0
UCI(KEPA) : I410-ECN-0101-2013-569-001139036