지원사업
학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
커뮤니티
연구자들이 자신의 연구와 전문성을 널리 알리고, 새로운 협력의 기회를 만들 수 있는 네트워킹 공간이에요.
논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE Journal of Semiconductor Technology and Science Vol.16 No.4
- 발행연도
- 2016.8
- 수록면
- 520 - 527 (8page)
이용수
초록· 키워드
오류제보하기
A new dual-loop digital delay-locked loop (DLL) using a hybrid (binary + sequential) search algorithm is presented to achieve both wide-range operation and high delay resolution. A new phase-interpolation range selector (PIRS) and a variable successive approximation register (VSAR) algorithm are adopted to resolve the boundary switching and harmonic locking problems of conventional digital DLLs. The proposed digital DLL, implemented in a 0.18-㎛ CMOS process, occupies an active area of 0.19 ㎟ and operates over a wide frequency range of 0.15–1.5 ㎓. The DLL dissipates a power of 11.3 ㎽ from a 1.8 V supply at 1 ㎓. The measured peak-to-peak output clock jitter is 24 ㎰ (effective pk-pk jitter = 16.5 ㎰) with an input clock jitter of 7.5 ㎰ at 1.5 ㎓. The delay resolution is only 2.2 ㎰.
목차
Abstract
Ⅰ. INTRODUCTION
Ⅱ. PROPOSED DUAL-LOOP DIGITAL DLL ARCHITECTURE
Ⅲ. BOUNDARY SWITCHING PROBLEM OF A DIGITAL DLL
Ⅳ. EXPERIMENTAL RESULTS
Ⅳ. CONCLUSION
REFERENCES
참고문헌 (12)
참고문헌 신청
[학술지(정기간행물)] - Y. Moon / 2000 / An all-analog multiphase delay-locked loop using a replica delay line for wide-range operation and low-jitter performance / IEEE J. Solid-State Circuits 35 (3) : 377 ~ 384
[학술지(정기간행물)] - S. Bae / 2005 / A VCDL-based 60-760MHz dual-loop DLL with infinite phaseshift capability and adaptive-bandwidth scheme / IEEE J. Solid-State Circuits 40 (5) : 1119 ~ 1129
[학술지(정기간행물)] - R. Yang / 2007 / A 40-550MHz harmonic-free all-Digital delay-locked loop using a variable SAR algorithm / IEEE J. Solid-State Circuits 42 (2) : 361 ~ 373
[학술지(정기간행물)] - T. Matano / 2003 / A 1-Gb/s/pin 512-Mb DDRII SDRAM using a digital DLL and a slew-ratecontrolled output buffer / IEEE J. Solid-State Circuits 38 (5) : 762 ~ 768
[학술지(정기간행물)] - L. Wang / 2010 / An Implementation of Fast-Locking and Wide-Range 11-bit Reversible SAR DLL / IEEE Trans. Circuits and Systems II 57 (6) : 421 ~ 425
[학술지(정기간행물)] - S. Bae / 2005 / A VCDL-based 60-760MHz dual-loop DLL with infinite phaseshift capability and adaptive-bandwidth scheme / IEEE J. Solid-State Circuits 40 (5) : 1119 ~ 1129
[학술지(정기간행물)] - R. Yang / 2007 / A 40-550MHz harmonic-free all-Digital delay-locked loop using a variable SAR algorithm / IEEE J. Solid-State Circuits 42 (2) : 361 ~ 373
[학술지(정기간행물)] - T. Matano / 2003 / A 1-Gb/s/pin 512-Mb DDRII SDRAM using a digital DLL and a slew-ratecontrolled output buffer / IEEE J. Solid-State Circuits 38 (5) : 762 ~ 768
[학술지(정기간행물)] - L. Wang / 2010 / An Implementation of Fast-Locking and Wide-Range 11-bit Reversible SAR DLL / IEEE Trans. Circuits and Systems II 57 (6) : 421 ~ 425
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UCI(KEPA) : I410-ECN-0101-2017-569-001108942