지원사업
학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
커뮤니티
연구자들이 자신의 연구와 전문성을 널리 알리고, 새로운 협력의 기회를 만들 수 있는 네트워킹 공간이에요.
논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE Journal of Semiconductor Technology and Science Vol.19 No.6
- 발행연도
- 2019.12
- 수록면
- 585 - 593 (9page)
- DOI
- 10.5573/JSTS.2019.19.6.585
이용수
초록· 키워드
오류제보하기
This paper presents a two-stage analog to digital converter (ADC) combined with cyclic and successive approximation register (SAR) architectures. A correlated level sampling (CLS) technique is implemented to reduce the DC gain requirement of the op-amp from 65 ㏈ to 35 ㏈. Moreover, a capacitor sharing technique is adopted to reduce the size of the op-amp load capacitors. The proposed ADC achieves both low-power consumption and a small chip area by means of the proposed structure. Furthermore, the conversion speed increases by operating both stages simultaneously. The ADC is fabricated using a 110 ㎚ complementary metal-oxide semiconductor (CMOS), and occupies a core area of 0.247 ㎟. The signal-to-noise-and-distortion ratio is 56.4 ㏈ with a 2.4-㎒ input. It consumes 2.17-㎽ of power from a 1.2-V supply voltage, and achieves an 80.4 fJ/step of power efficiency.
목차
Abstract
Ⅰ. INTRODUCTION
Ⅱ. ARCHITECTURE
Ⅲ. CIRCUIT DESCRIPTION
Ⅳ. MEASUREMENT RESULTS
Ⅴ. CONCLUSIONS
REFERENCES
참고문헌 (12)
참고문헌 신청
Y.-H. Ou-Yang, and K.-T. Tang, “An Energy- Efficient SAR ADC With Event-Triggered Error Correction,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 66, no. 5, pp. 723- 727, 2019.
H. Zhang, H. Zhang, Y. Song, and R. Zhang, “A 10- Bit 200-kS/s 1.76-μW SAR ADC With Hybrid CAP-MOS DAC for Energy-Limited Applications,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 66, no. 5, pp. 1716-1727, 2019.
M. Liu, A. H. M. van Roermund, and P. Harpe, “A 10-b 20-MS/s SAR ADC With DAC-Compensated Discrete-Time Reference Driver,” IEEE Journal of Solid-State Circuits, vol. 54, no. 2, pp. 417-427, 2019.
F. Rabuske, T. Rabuske, and J. Fernandes, “A 5-bit 300?900-MS/s 0.8?1.2-V Supply Voltage ADC With Background Self-Calibration,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 64, no. 1, pp. 1-5, 2017.
J. J. Mao, M. Q. Guo, S. W. Sin, and R. P. Martins, “A 14-Bit Split-Pipeline ADC With Self-Adjusted Opamp-Sharing Duty-Cycle and Bias Current,” Ieee Transactions on Circuits and Systems Ii- Express Briefs, vol. 65, no. 10, pp. 1380-1384, Oct, 2018.
H. Zhang, H. Zhang, Y. Song, and R. Zhang, “A 10- Bit 200-kS/s 1.76-μW SAR ADC With Hybrid CAP-MOS DAC for Energy-Limited Applications,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 66, no. 5, pp. 1716-1727, 2019.
M. Liu, A. H. M. van Roermund, and P. Harpe, “A 10-b 20-MS/s SAR ADC With DAC-Compensated Discrete-Time Reference Driver,” IEEE Journal of Solid-State Circuits, vol. 54, no. 2, pp. 417-427, 2019.
F. Rabuske, T. Rabuske, and J. Fernandes, “A 5-bit 300?900-MS/s 0.8?1.2-V Supply Voltage ADC With Background Self-Calibration,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 64, no. 1, pp. 1-5, 2017.
J. J. Mao, M. Q. Guo, S. W. Sin, and R. P. Martins, “A 14-Bit Split-Pipeline ADC With Self-Adjusted Opamp-Sharing Duty-Cycle and Bias Current,” Ieee Transactions on Circuits and Systems Ii- Express Briefs, vol. 65, no. 10, pp. 1380-1384, Oct, 2018.
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