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논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE Journal of Semiconductor Technology and Science Vol.20 No.2
- 발행연도
- 2020.4
- 수록면
- 158 - 162 (5page)
- DOI
- 10.5573/JSTS.2020.20.2.158
이용수
초록· 키워드
오류제보하기
This paper investigates the output characteristics in tunnel field-effect transistor (TFET). The nonlinear current (NLC) in output characteristics has remained as a critical issue for operating at low drain bias (V<SUB>DS</SUB>). In this paper, the energy band diagrams and charge density distributions are analyzed to confirm the relation between output current and V<SUB>DS</SUB>, based on the technology computer-aided design (TCAD) simulations. Then, the NLC is analyzed as a channel potential pinning which occurs from the charges supplied from the drain to the channel.
목차
Abstract
I. INTRODUCTION
II. DEVICE AND SIMULATION
III. RESULTS AND DISCUSSION
V. CONCLUSION
REFERENCES
참고문헌 (16)
참고문헌 신청
W. Y. Choi, B.-G. Park, J. D. Lee, and T.-J. K. Liu, “Tunneling field-effect transistors (TFETs) with subthreshold swing (SS) less than 60 mV/dec,” IEEE Electron Device Letters, vol. 28, no. 8, pp. 743-745, Aug. 2007. doi: 10.1109/LED.2007.901273
P.-Y. Wang and B.-Y. Tsui, “Band engineering to improve average subthreshold swing by suppressing low electric field band-to-band tunneling with epitaxial tunnel layer tunnel FET structure,” IEEE Transactions on Nanotechnology, Vol. 15, no. 1, pp. 74-79, Jan. 2016. doi: 10.1109/TNANO.2015.2501829
S. W. Kim, W. Y. Choi, H. Kim, M. C. Sun, H. W. Kim and B.-G. Park, “Investigation on hump effects of L-shaped tunneling filed-effect transistors,” IEEE Silicon Nanoelectronics Workshop (SNW), Honolulu, HI, 2012, pp. 1-2. doi: 10.1109/SNW.2012.6243306
A. Mishra, M. Pattanaik and V. Sharma, “Double gate vertical tunnel FET for hybrid CMOS-TFET based low standby power logic circuits,” Annual International Conference on Emerging Research Areas and International Conference on Microelectronics, Communications and Renewable Energy, Kanjirapally, 2013, pp. 1-4. doi: 10.1109/AICERA-ICMiCR.2013.6575992
J. Knoch, “Chapter Eight - nanowire tunneling field-effect transistors,” Semiconductors and Semimetals, Vol. 94, pp. 273-295, 2016, http://dx.doi.org/10.1016/bs.semsem.2015.09.005
P.-Y. Wang and B.-Y. Tsui, “Band engineering to improve average subthreshold swing by suppressing low electric field band-to-band tunneling with epitaxial tunnel layer tunnel FET structure,” IEEE Transactions on Nanotechnology, Vol. 15, no. 1, pp. 74-79, Jan. 2016. doi: 10.1109/TNANO.2015.2501829
S. W. Kim, W. Y. Choi, H. Kim, M. C. Sun, H. W. Kim and B.-G. Park, “Investigation on hump effects of L-shaped tunneling filed-effect transistors,” IEEE Silicon Nanoelectronics Workshop (SNW), Honolulu, HI, 2012, pp. 1-2. doi: 10.1109/SNW.2012.6243306
A. Mishra, M. Pattanaik and V. Sharma, “Double gate vertical tunnel FET for hybrid CMOS-TFET based low standby power logic circuits,” Annual International Conference on Emerging Research Areas and International Conference on Microelectronics, Communications and Renewable Energy, Kanjirapally, 2013, pp. 1-4. doi: 10.1109/AICERA-ICMiCR.2013.6575992
J. Knoch, “Chapter Eight - nanowire tunneling field-effect transistors,” Semiconductors and Semimetals, Vol. 94, pp. 273-295, 2016, http://dx.doi.org/10.1016/bs.semsem.2015.09.005
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