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논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 대한전기학회 Journal of Electrical Engineering & Technology Journal of Electrical Engineering & Technology Vol.12 No.5
- 발행연도
- 2017.9
- 수록면
- 2,014 - 2,020 (7page)
이용수
이 논문의 연구 히스토리 (4)
2021
Compact Capacitance Model of L-Shape Tunnel Field-Effect Transistors for Circuit Simulation
Yun Seop Yu
,
Fa
,
az Najam
Journal of information and communication convergence engineering
2021.12
학술저널
Compact Capacitance Model of L-Shaped Tunneling Field-effect Transistors
Yun Seop Yu
,
Fa
,
az Najam
INTERNATIONAL CONFERENCE ON FUTURE INFORMATION & COMMUNICATION ENGINEERING
2021.02
학술대회자료
2017
Compact Current Model of Single-Gate/Double-Gate Tunneling Field-Effect Transistors
Yun Seop Yu
,
Fa
,
az Najam
Journal of Electrical Engineering & Technology
2017.09
학술저널
Capacitance model of Single-Gate Tunneling Field-Effect Transistors for Circuit Simulation
Yun Seop Yu
,
Hyung-Kun Pa
,
k
INTERNATIONAL CONFERENCE ON FUTURE INFORMATION & COMMUNICATION ENGINEERING
2017.06
학술대회자료
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- 이 논문의 연구 히스토리 확인하기
초록· 키워드
오류제보하기
A compact current model applicable to both single-gate (SG) and double-gate (DG) tunneling field-effect transistors (TFETs) is presented. The model is based on Kane’s band-to-band tunneling (BTBT) model. In this model, the well-known and previously-reported quasi-2-D solution of Poisson’s equation is used for the surface potential and length of the tunneling path in the tunneling region. An analytical tunneling current expression is derived from expressions of derivatives of local electric field and surface potential with respect to tunneling direction. The previously reported correction factor with three fitting parameters, compensating for superlinear onset and saturation current with drain voltage, is used. Simulation results of the proposed TFET model are compared with those from a technology computer-aided-design (TCAD) simulator, and good agreement in all operational bias is demonstrated. The proposed SG/DG-TFET model is developed with Verilog-A for circuit simulation. A TFET inverter is simulated with the Verilog-A SG/DG-TFET model in the circuit simulator; the model exhibits typical inverter characteristics, thereby confirming its effectiveness.
목차
Abstract
1. Introduction
2. Model Development
3. Model Validation
4. Conclusion
References
참고문헌 (19)
참고문헌 신청
H. Lu and A. Seabaugh, “Tunnel field-effect transistors: State-of-the-art,” IEEE J. Electron Devices Soc., vol. 2, no. 4, pp.44-49, Apr. 2014.
A. M. Ionescu and H. Riel, “Tunnel field-effect transistors as energy efficient electronic switches,” Nature, vol. 479, no. 7373, pp. 329-337, Nov. 2011.
Q. Huang, R. Jia, C. Chen, H. Zhu, L. Guo, J. Wang, J. Wang, C. Wu, R. Wang, W. Bu, J. Kang, W. Wang, H. Wu, S.-W. Lee, Y. Wang, and R. Huang, “First foundry platform of complementary tunnel-FETs in CMOS baseline technology for ultralow-power IoT applications: Manufacturability, variability and technology roadmap,” in Proc. IEEE Int. Electron Devices Meeting (IEDM), Washington, DC, USA, Dec. 2015, pp. 22.2.1-22.2.4, doi: 10.1109/IEDM.2015.7409756.
M. Lanuzza, S. Strangio, F. Crupi, P. Palestri, and D. Esseni, “Mixed Tunnel-FET/MOSFET Level Shifters: a new proposal to extend the Tunnel-FET application domain,” IEEE Trans. Electron Devices, vol. 62, no. 12, pp. 3973-3979, Dec. 2015.
D. H. Morris, U. E. Avci, R. Rios, and I. A. Young, “Design of low voltage tunneling-FET logic circuits considering asymmetric conduction characteristics,” IEEE J. Emerg. Sel. Topics Circuits Syst., vol. 4, no. 4, pp. 380-388, Dec. 2014.
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