지원사업
학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
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논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE Journal of Semiconductor Technology and Science Vol.20 No.4
- 발행연도
- 2020.8
- 수록면
- 326 - 342 (17page)
- DOI
- 10.5573/JSTS.2020.20.4.326
이용수
초록· 키워드
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This paper presents the design of a 5-channel receiver for ocean acoustic measurement in very noisy environments. When measuring distances in the ocean through sonar, the input signal level to the receiver can change drastically depending on the distance between the transmitter and objects. Thus, a receiver with low sensitivity and a wide dynamic range is proposed in this work. In order to minimize the Input-Referred (IR) noise for the high sensitivity of the receiver, a low noise pre-amplifier is proposed and implemented, ultimately achieving a noise of 29.6 nV/√Hz at 50 kHz. In addition, a Sigma-Delta Analogto- Digital Converter (SD ADC) with variable sampling rates is proposed by using the clock splitting technique in the Sigma-Delta Modulator (SDM) core. In addition, the decimation factor of the digital filter placed after the SDM in the SD ADC can be controlled so as to reduce the power consumption. Through the use of these techniques in the SD ADC, we can implement reconfigurable sampling rates from 1.5 MS/s to 12.5 MS/s with low power consumption. In order to overcome the limitation of the number of pins for multi-channel application, a Parallel-to-Serial (P2S) interface is proposed and designed in the receiver. The 5-channel receiver in this paper is implemented in a 0.18 μm CMOS process and the die area is 14.44 mm2. The total power consumption of this chip under a supply voltage of 2.4 V is 46.8 mW. The measured sensitivity and dynamic range are - 100 dBV and 100 dB, respectively. The measured SNDR at the output of the SD ADC is 82.02 dB when the input signal frequency and sampling frequency are 7 kHz and 6.25 Msps, respectively. The maximum phase error between five channels is measured to be ±0.8 °.
목차
Abstract
I. INTRODUCTION
II. PROPOSED LOW NOISE RECEIVER ARCHITECTURE FOR SONAR SENSOR
III. BUILDING BLOCKS
IV. EXPERIENCE RESULT
V. CONCLUSIONS
REFERENCES
참고문헌 (21)
참고문헌 신청
Kim, S.; Na, S.-I.; Yang, Y.; Kim, S. A 2-MHz BW 82-dB DR Continuous-Time Delta-Sigma Modulator With a Capacitor-Based Voltage DAC for ELD Compensation. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2018, pp. 1-8, 10.1109/TVLSI.2018.2841058.
Weng, C.-H.; Lin, Y.-Y.; Lin, T.-H. A 1-V 5-MHz Bandwidth 68.3-dB SNDR Continuous-Time Delta-Sigma Modulator With a Feedback-Assisted Quantizer. IEEE Transactions on Circuits and Systems I: Regular Papers , 2017, 64, 1085-1093.
Kim, T.-W.; Han, C.; Maghari, N. A 7.2 mW 75.3 dB SNDR 10 MHz BW CT Delta-Sigma Modulator Using Gm-C-Based Noise-Shaped Quantizer and Digital Integrator. IEEE Journal of Solid-State Circuits, 2016, 51, 1840 - 1850.
Chu, C.; Bruckner, T.; Kauffman, J.-G. Analysis and design of high speed/high linearity continuous time delta-sigma modulator; 2013 IEEE International Symposium on Circuits and Systems, Beijing, China, 19-23 May 2013; pp. 1268-1271.
Caldwell, T.; Shibata H. High-Speed Oversampled Continuous-Time Analog-to-Digital Converters; 2017 IEEE 60th International Midwest Symposium on Circuits and Systems; Boston MA, USA, 6-9 August 2017; pp. 1001-1004.
Weng, C.-H.; Lin, Y.-Y.; Lin, T.-H. A 1-V 5-MHz Bandwidth 68.3-dB SNDR Continuous-Time Delta-Sigma Modulator With a Feedback-Assisted Quantizer. IEEE Transactions on Circuits and Systems I: Regular Papers , 2017, 64, 1085-1093.
Kim, T.-W.; Han, C.; Maghari, N. A 7.2 mW 75.3 dB SNDR 10 MHz BW CT Delta-Sigma Modulator Using Gm-C-Based Noise-Shaped Quantizer and Digital Integrator. IEEE Journal of Solid-State Circuits, 2016, 51, 1840 - 1850.
Chu, C.; Bruckner, T.; Kauffman, J.-G. Analysis and design of high speed/high linearity continuous time delta-sigma modulator; 2013 IEEE International Symposium on Circuits and Systems, Beijing, China, 19-23 May 2013; pp. 1268-1271.
Caldwell, T.; Shibata H. High-Speed Oversampled Continuous-Time Analog-to-Digital Converters; 2017 IEEE 60th International Midwest Symposium on Circuits and Systems; Boston MA, USA, 6-9 August 2017; pp. 1001-1004.
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