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논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE Journal of Semiconductor Technology and Science Vol.22 No.2
- 발행연도
- 2022.4
- 수록면
- 53 - 60 (8page)
- DOI
- 10.5573/JSTS.2022.22.2.53
이용수
초록· 키워드
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In Elliptic Curve Cryptography (ECC), modular multiplication in a finite field is a resource-consuming operation. The design of an efficient multiplier for ECC implementation in FPGA is an ever-evolving research problem. In this paper, we provide an efficient implementation of ECC for GF (2<SUP>233</SUP>) in FPGA. We propose a hybrid Karatsuba multiplier which is found to be occupying lesser slices compared to other optimized Karatsuba multiplier in [1]. This, in turn, amends the efficiency of the ECC processor in the FPGA platform. The proposed processor is implemented in ZedBoard containing Xilinx XC7Z020-1CLG484C Zynq-7000 AP SoC. In comparison with other similar works, the implementation results of ECC show consequential competitiveness in hardware efficiency and we obtain an efficient multiplier and ECC processor realized in FPGA. From the application point of view, ZedBoard has an ARM Processor and hence this can be utilized in vehicle On-Board Units (OBU) because of its lightweight properties.
목차
Abstract
Ⅰ. INTRODUCTION
Ⅱ. MATHEMATICAL BACKGROUND
Ⅲ. MULTIPLICATION METHODS
Ⅳ. OUR PROPOSED WORK
Ⅴ. IMPLEMENTATION RESULTS AND ANALYSIS
Ⅵ. CONCLUSION
REFERENCES
참고문헌 (19)
참고문헌 신청
Chester Rebeiro and Debdeep Mukhopadhyay, “Hybrid Masked Karatsuba Multiplier For Gf(2233)”, Proceedings of the 11th IEEE VLSI Design and Test Symposium, Kolkata, VLSI Society of India., no. 1, 2007, pp. 379-387.
Ravi Kishore Kodali, Siva Kumar, Vishal Jain and Boppana Lakshmi, “Hybrid Multiplier for ECC”, IEEE Recent Advances in Intelligent Computational Systems (RAICS), December 2015, pp. 65-70
Rakesh K. Kadu and Dattatraya S. Adane, “Hardware Implementation of Efficient Elliptic Curve Scalar Multiplication using Vedic Multiplier”, International Journal of Communication Networks and Information Security (IJCNIS), Vol. 11, No. 2, August 2019, pp. 270-277.
Steffen Peter and Peter LangendOrfer, “An Efficient Polynomial Multiplier in GF(2m) and its Application to ECC Designs”, Design, Automation & Test in Europe Conference & Exhibition, Nice, 2007, pp. 1-6
Jiafeng Xie, Pramod Kumar Meher, Mingui Sun, Yuecheng Li, Bo Zeng, and Zhi-Hong Mao, “Efficient FPGA Implementation of Low-Complexity Systolic Karatsuba Multiplier Over GF(2m) Based on NIST Polynomials”, IEEE Transactions On Circuits And Systems–I: Regular Papers, Vol. 64, No. 7, July 2017, pp. 1815-1825
Ravi Kishore Kodali, Siva Kumar, Vishal Jain and Boppana Lakshmi, “Hybrid Multiplier for ECC”, IEEE Recent Advances in Intelligent Computational Systems (RAICS), December 2015, pp. 65-70
Rakesh K. Kadu and Dattatraya S. Adane, “Hardware Implementation of Efficient Elliptic Curve Scalar Multiplication using Vedic Multiplier”, International Journal of Communication Networks and Information Security (IJCNIS), Vol. 11, No. 2, August 2019, pp. 270-277.
Steffen Peter and Peter LangendOrfer, “An Efficient Polynomial Multiplier in GF(2m) and its Application to ECC Designs”, Design, Automation & Test in Europe Conference & Exhibition, Nice, 2007, pp. 1-6
Jiafeng Xie, Pramod Kumar Meher, Mingui Sun, Yuecheng Li, Bo Zeng, and Zhi-Hong Mao, “Efficient FPGA Implementation of Low-Complexity Systolic Karatsuba Multiplier Over GF(2m) Based on NIST Polynomials”, IEEE Transactions On Circuits And Systems–I: Regular Papers, Vol. 64, No. 7, July 2017, pp. 1815-1825
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