Synthesis of Complementary Pass Gate Network for a Quaternary Logic Function and Its Application

Kyu Ik Sohng ,  Michitaka Kameyama ,  Tatsuo Higuchi

JTC-CSCC : Joint Technical Conference on Circuits Systems, Computers and Communications

1988 .01

Complementary Pass-Transistor Logic 회로의 모델링 및 최적 사이징 ( The Modeling and Optimal Sizing of Complementary Pass-Transistor Logic Circuits )

이영중 ,  정항근

한국통신학회 학술대회논문집

1997 .01

Design of Quaternary Logic gate Using Double Pass-transistor Logic with neuron MOS Threshold gate

Soo Jin Pa ,  k ,  Byoung Hee Yoon 외 1명

ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications

2003 .07

[소자부품최적화] Complementary Pass-transistor Logic 회로의 모델링 및 최적 사이징

이영중 ,  정항근

한국통신학회 학술대회논문집

1997 .11

New Dynamic Logic Gate Design Method for Improved TFT Circuit Performance

Jeong ,  Ju-Young ,  Kim 외 1명

Journal of information display

2005 .01

Logic Gate간의 상호 연결도 검증 ( Verification of Logic Gate Interconnectivity )

정자춘 ,  경종민

대한전자공학회 학술대회

1985 .01

LOGIC-CHECKER : A CORRECTING FUNCTION FOR GATE ERRORS IN LOGIC SIMULATION AND ITS IMPLEMENTATION

Satoshi Wakabayashi ,  Hi ,  oyuki Ishikawa 외 1명

JTC-CSCC : Joint Technical Conference on Circuits Systems, Computers and Communications

1989 .01

By Pass System

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시멘트

2000 .01

Comparative Study on the Structural Dependence of Logic Gate Delays in Double-Gate and Triple-Gate FinFETs

Kwan Young Kim ,  Jae Man Jang ,  Dae Youn Yun 외 2명

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE

2010 .06

A Novel Charge Recovery Logic Structure with Complementary Pass-transistor Network

Jingyang Li ,  Yimeng Zhang ,  Tsutomu Yoshiha 외 1명

대한전자공학회 ISOCC

2012 .11

3-Level Gate Drive Design

노재석 ,  배기훈 ,  강호현 외 1명

전력전자학회 학술대회 논문집

2018 .07

A Rule-Based System for VLSI Gate-level Logic Optimization

Seong Bong Lee ,  Jong Hwa Chong

JTC-CSCC : Joint Technical Conference on Circuits Systems, Computers and Communications

1988 .01

A Universal Gate for Combinational Design of QCA Circuits

Young Bok Kim ,  Yong-Bin Kim ,  F. Lomba 외 1명

대한전자공학회 ISOCC

2009 .11

Multiple-Valued Logics and Classification Criteria

Václav Pinkava

한국지능시스템학회 논문지

1993 .03

단일 전자 논리 회로를 위한 단일 전자 상보 논리 게이트의 설계

정문영 ,  정윤하 ,  김대만

대한전자공학회 학술대회

1996 .11

New Logic Simulation by the Gate-Level Waveform Relaxation Method

Ki Jun Lee

JTC-CSCC : Joint Technical Conference on Circuits Systems, Computers and Communications

1988 .01

High Performance Organic Complementary Circuits with a Low-k and High-Tg Polymer Gate Dielectric

장재영 ,  박찬언

한국고분자학회 학술대회 연구논문 초록집

2009 .10

Junctionless Sandwiched-gate Logic Design using Novel Device Structure

Myunghwan Ryu ,  Youngmin Kim

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE

2018 .08

Visual Logic Modeling Environment for Network Problems

안영신 ,  최인준 ,  서의호

대한산업공학회 춘계공동학술대회 논문집

1992 .05

Multiple-Valued Logic Neural Networks

Ali Massoud Haida ,  Mititada Mo ,  isue

JTC-CSCC : Joint Technical Conference on Circuits Systems, Computers and Communications

1993 .01