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논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- Korean Institute of Information Scientists and Engineers Journal of Electrical Engineering and Information Science Journal of Electrical Engineering and Information Science Vol.3 No.2
- 발행연도
- 1998.4
- 수록면
- 261 - 266 (6page)
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This paper describes the fabrication and characterization of dual-polysilicon gated surface channel 0.1㎛ CMOSFETs using BF_2 and arsenic as channel dopants. We have used an LDD structure and 40 Å gate oxide as an insulator. To suppress short channel effects down to 0.1㎛ channel length, shallow source/drain extensions implemented by low energy implantation and SSR(Super Steep Retrograde) channel structure were used. The threshold voltages of fabricated CMOSFETs are 0.6V. The maximum transconductance of nMOSFET is 315 μS/㎛, and that of pMOSFET is 156 μS/㎛. The drain saturation current of 418 μA/㎛, 187 μA/㎛ are obtained. Subthreshold swing is 85mV/dec and 88mV/dec, respectively. DIBL(Drain Induced Barrier Lowering) is below 100mV. In the device with 2000Å thick gate polysilicon, depletion in polysilicon near the gate oxide results in an increase of equivalent gate oxide thickness and degradation of device characteristics. The gate delay time is measured to be 336psec at operation voltage of 2V.
목차
Abstract
Ⅰ. Introduction
Ⅱ. Fabrication
Ⅲ. Device Characteristics
Ⅳ. Conclusion
Acknowledgment
References
저자소개
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