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논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE Journal of Semiconductor Technology and Science Vol.8 No.2
- 발행연도
- 2008.6
- 수록면
- 156 - 163 (8page)
이용수
초록· 키워드
오류제보하기
We proposed a new p?/n? gate locallyseparated- channel (LSC) bulk FinFET which has vertically formed oxide region in the center of fin body, and device characteristics were optimized and compared with that of normal channel (NC) FinFET. Key device characteristics were investigated by changing length of n<SUP>?</SUP> poly-Si gate (L<SUB>s</SUB>), the material filling the trench, and the width and length of the trench at a given gate length (L<SUB>g</SUB>). Using 3-dimensional simulations, we confirmed that short-channel effects were properly suppressed although the fin width was the same as that of NC device. The LSC device having the trench non-overlapped with the source/drain diffusion region showed excellent I<SUB>off</SUB> suitable for sub-50 nm DRAM cell transistors. Design of the LSC devices were performed to get reasonable L<SUB>s</SUB>/L<SUB>g</SUB> and channel fin width (W<SUB>cfin</SUB>) at given L<SUB>g</SUB>s of 30 ㎚, 40 ㎚, and 50 ㎚.
목차
Abstract
Ⅰ. INTRODUCTION
Ⅱ. DEVICE STRUCTURE
Ⅲ. DEVICE SIMULATION RESULTS
Ⅳ. CONCLUSIONS
ACKNOWLEDGMENTS
REFERENCES
참고문헌 (15)
참고문헌 신청
1. [학술지(정기간행물)] - R. Katsumata / 2003 / Fin-Array-FET on bulk silicon for sub-100 nm trench capacitor DRAM / in VLSI Symp. Tech. Dig : 61 ~ 62
2. [학술지(정기간행물)] - C. H. Lee / 2004 / Novel body tied FinFET cell array transistor DRAM with negative word line operation for sub 60nm technology and beyond / in VLSI Symp. Tech. Dig : 130 ~ 131
3. [학술지(정기간행물)] - D. H. Lee / 2003 / Fin-channel-array transistor (FCAT) featuring sub-70nm low power and high performance DRAM / in IEDM Tech. Dig : 407 ~ 410
4. [학술지(정기간행물)] - C. Lee / 2004 / Enhanced data retention of damascene-finFET DRAM with local channel implantation and <100> fin surface orientation engineering / IEDM Tech. Dig : 61 ~ 64
5. [학술지(정기간행물)] - Y. S. Kim / 2006 / Fabrication and electrical properties of local damascene FinFET cell array in sub-60nm feature sized DRAM / Journal of Semiconductor Technology and Science 6 (2) : 61 ~ 66
2. [학술지(정기간행물)] - C. H. Lee / 2004 / Novel body tied FinFET cell array transistor DRAM with negative word line operation for sub 60nm technology and beyond / in VLSI Symp. Tech. Dig : 130 ~ 131
3. [학술지(정기간행물)] - D. H. Lee / 2003 / Fin-channel-array transistor (FCAT) featuring sub-70nm low power and high performance DRAM / in IEDM Tech. Dig : 407 ~ 410
4. [학술지(정기간행물)] - C. Lee / 2004 / Enhanced data retention of damascene-finFET DRAM with local channel implantation and <100> fin surface orientation engineering / IEDM Tech. Dig : 61 ~ 64
5. [학술지(정기간행물)] - Y. S. Kim / 2006 / Fabrication and electrical properties of local damascene FinFET cell array in sub-60nm feature sized DRAM / Journal of Semiconductor Technology and Science 6 (2) : 61 ~ 66
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