지원사업
학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
커뮤니티
연구자들이 자신의 연구와 전문성을 널리 알리고, 새로운 협력의 기회를 만들 수 있는 네트워킹 공간이에요.
논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 발행연도
- 2015.1
- 수록면
- 41 - 45 (5page)
이용수
초록· 키워드
오류제보하기
From 20nm technology node, the finFET has become standard device for ULSI's. However, the finFET process made stacking gate non-volatile memory obsolete. Some reported capacitor-less DRAM structure by utilizing the FBE. We present possible non-volatile memory device structure similar to the dual gate MOSFET. One of the gates is left floating. Since body of the finFET is only 40nm thick, control gate bias can make electron tunneling through the floating gate oxide which sits across the body. For programming, gate is biased to accumulation mode with few volts. Simulation results show that the programming electron current flows at the interface between floating gate oxide and the body. It also shows that the magnitude of the programming current can be easily controlled by the drain voltage. Injected electrons at the floating gate act similar to the body bias which changes the threshold voltage of the device.
목차
등록된 정보가 없습니다.
참고문헌 (8)
참고문헌 신청
Jacques Gautier' / 1995 / BODY CHARGE RELATED TRANSIENT EFFECTS IN FLOATING BODY SO1 NMOSFET’s / IEDM ’95 :623~626
S. Okhonin / 2002 / A capacitor-less 1T-DRAM cell / IEEE Electron Device Lett 23(2):85~87
E. Yoshida / 2003 / A design of a capacitorless 1T-DRAM cell using gate-induced drain leakage (GIDL) current for low-power and high-speed embedded memory / IEDM Tech. Dig :37.6.1~37.6.4
T. Tanaka / 2004 / Scalability study on a capacitorless 1T-DRAM: From single-gate PD-SOI to double-gate FinDRAM / IEDM Tech. Dig :919~922
Takeshi Hamamoto / 2008 / Overview and Future Challenges of Floating Body RAM (FBRAM) Technology for 32nm Technology Node and Beyond / ESSDERC :25~29
S. Okhonin / 2002 / A capacitor-less 1T-DRAM cell / IEEE Electron Device Lett 23(2):85~87
E. Yoshida / 2003 / A design of a capacitorless 1T-DRAM cell using gate-induced drain leakage (GIDL) current for low-power and high-speed embedded memory / IEDM Tech. Dig :37.6.1~37.6.4
T. Tanaka / 2004 / Scalability study on a capacitorless 1T-DRAM: From single-gate PD-SOI to double-gate FinDRAM / IEDM Tech. Dig :919~922
Takeshi Hamamoto / 2008 / Overview and Future Challenges of Floating Body RAM (FBRAM) Technology for 32nm Technology Node and Beyond / ESSDERC :25~29
함께 읽어보면 좋을 논문
논문 유사도에 따라 DBpia 가 추천하는 논문입니다. 함께 보면 좋을 연관 논문을 확인해보세요!
-
Floating Gate 기반 Logic-in-Memory 소자 최적화
대한전자공학회 학술대회
2022 .06
-
3-D Simulation of Nanoscale SOI n-FinFET at a Gate Length of 8 nm Using ATLAS SILVACO
Transactions on Electrical and Electronic Materials
2015 .01
-
Floating Gate 기반 Logic in Memory 소자 Compact Modeling
대한전자공학회 학술대회
2022 .06
-
Analysis of Electrical Characteristics Changes Due to Physical Parameter Variations in Dual-Gate Feedback Field Effect Transistor
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE
2025 .02
-
Ⅲ-Ⅴ화합물 반도체 기반 Triple Gate MOSFET과 Gate All Around Nanowire NMOSFET의 성능 비교
대한전자공학회 학술대회
2015 .11
-
Multi-gate BCAT Structure and Select Word-line Driver in DRAM for Reduction of GIDL
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE
2022 .12
-
Exploration of Linearity Analysis in Nanotube GAA MOSFET Through Simulation-Based Study Utilizing Multi-Material Gate Technique
Transactions on Electrical and Electronic Materials
2024 .08
-
Comparative Study of Single and Double Gate All Around Cylindrical FET Structures for High-K Dielectric Materials
Transactions on Electrical and Electronic Materials
2021 .08
-
Linearity Analysis of MoTe 2 -FET based Single Transistor AND Gate Using Non-Equilibrium Green’s Function
Transactions on Electrical and Electronic Materials
2022 .04
-
Power Switch MOSFET의 Gate를 구동하기 위한 Gate Driver의 Power Loss 분석
대한전자공학회 학술대회
2024 .06
-
Comparison of GIDL mechanism between MOSFET and FinFET
ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications
2015 .06
-
Investigation of Junction-less Tunneling Field Effect Transistor (JL-TFET) with Floating Gate
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE
2017 .02
-
Analysis of Tunneling Current for Gate Oxide Thickness of Sub-10 nm Asymmetric Double Gate MOSFET
INTERNATIONAL CONFERENCE ON FUTURE INFORMATION & COMMUNICATION ENGINEERING
2015 .06
-
진공 게이트 스페이서를 지니는 Bulk FinFET의 단채널효과 억제를 위한 소자구조 최적화 연구
전기전자재료학회논문지
2022 .11
-
플랜트 사업의 리스크 관리를 위한 gate review 수행 방안
대한기계학회 춘추학술대회
2021 .11
-
MOSFET에서 다결정 실리콘 게이트 막의 도핑 농도가 신뢰성에 미치는 영향
전기전자재료학회논문지
2018 .02
-
3-Level Gate Drive Design
전력전자학회 학술대회 논문집
2018 .07
-
Top and Bottom Gate Voltage Dependent Tunneling Current of Asymmetric DGMOSFET
INTERNATIONAL CONFERENCE ON FUTURE INFORMATION & COMMUNICATION ENGINEERING
2015 .06
-
Design and Analysis of Gate Engineered Dual Material Gate Double Gate Impact Ionization Metal Oxide Semiconductor
Transactions on Electrical and Electronic Materials
2019 .01
이 논문의 저자 정보
최근 본 자료
댓글(0)
0