지원사업
학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
커뮤니티
연구자들이 자신의 연구와 전문성을 널리 알리고, 새로운 협력의 기회를 만들 수 있는 네트워킹 공간이에요.
이용수
Abstract
1. Introduction
2. Proposed strategy
3. Encoding /decoding of scan vectors by considering low power dissipation and high compression
4. Experimental Results
5. Conclusion
References
논문 유사도에 따라 DBpia 가 추천하는 논문입니다. 함께 보면 좋을 연관 논문을 확인해보세요!
Efficient Test Data Compression and Low Power Scan Testing in SoCs
[ETRI] ETRI Journal
2003 .10
A New Low Power Scan Architecture Considering Test Data Compression
대한전자공학회 ISOCC
2006 .10
A New Test Data Compression for Low Power Test
대한전자공학회 학술대회
2005 .05
Low Power Scan Chain Reordering Method with Limited Routing Congestion for Code-based Test Data Compression
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE
2016 .10
System-On-a-Chip(SOC)에 대한 효율적인 테스트 데이터 압축 및 저전력 스캔 테스트
전자공학회논문지-SD
2002 .12
Low-Power Scan Testing Using Test Vector Reordering for System-on-a-Chip
대한전자공학회 ISOCC
2005 .10
Efficient Parallel Scan Test Technique for Cores on AMBA-based SoC
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE
2014 .06
Efficient Low-power Scan Test Method based on Exclusive Scan and Scan Chain Reordering
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE
2020 .08
Efficient Test Data Compression Using Transition Directed Run-length Code in System-on-a-Chip
대한전자공학회 ISOCC
2005 .10
A Low Power Scan Design Architecture
대한전자공학회 ISOCC
2004 .10
Modeling and Analysis of On-chip and Off-Chip Power Supply Network
ICVC : International Conference on VLSI and CAD
1997 .01
A New Scan Slice Encoding Scheme with Flexible Code for Test Data Compression
대한전자공학회 ISOCC
2010 .11
테스트 비용 절감을 위한 스캔 체인 기반의 저전력 테스트 패턴 압축 기술
대한전자공학회 학술대회
2013 .07
Operation about Multiple Scan Chains based on System-on-Chip
대한전자공학회 ISOCC
2008 .11
Chip Package-System Co-Design
대한전자공학회 ISOCC
2009 .11
A Low Power Mixed Mode Motion Estimation for Data Compression
대한전자공학회 기타 간행물
2001 .11
Protein chip has become an efficient method in the area of diagnostics
한국생물공학회 학술대회
2008 .04
Four-Dynamic Partitioning of Scan Chains for Low Peak Power
ICEIC : International Conference on Electronics, Informations and Communications
2010 .06
An Efficient Delay Test Method Using Boundary-Scan Architecture
ICVC : International Conference on VLSI and CAD
1993 .01
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