지원사업
학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
커뮤니티
연구자들이 자신의 연구와 전문성을 널리 알리고, 새로운 협력의 기회를 만들 수 있는 네트워킹 공간이에요.
논문 기본 정보
- 자료유형
- 학술대회자료
- 저자정보
- 발행연도
- 2010.11
- 수록면
- 217 - 220 (4page)
이용수
초록· 키워드
오류제보하기
As the design for testability (DFT) is essential in the semiconductor manufacturing, the scan-based architecture is widely used to decrease the test complexity of a chip. However, the scan-based architecture requires high test cost such as the test data volume and the test time. In order to alleviate the test cost problem of the scan-based architecture, a lot of test data compression schemes using the scan slice encoding have been presented. In this paper, we propose a new scan slice encoding scheme with flexible code for test data compression. The proposed scheme fully utilizes the flexible code as the control code or the data code. The flexible code provides supplementary encoding mode without additional control code. As a result, the test cost is significantly reduced by the various encoding mode with low test equipment pin overhead. The experiment results based on ISCAS’89 benchmark circuits show that the test data
volume and the test time is reduced up to 82% compared with the original data.
volume and the test time is reduced up to 82% compared with the original data.
목차
Abstract
Ⅰ. INTRODUCTION
Ⅱ. PROPOSED TEST DATA COMPRESSION SCHEME
Ⅲ. PROPOSED DECOMPRESSION ARCHITECTURE
Ⅳ. EXPERIMENTAL RESULTS
Ⅴ. CONCLUSION
ACKNOWLEDGMENT
REFERENCES
참고문헌 (0)
참고문헌 신청함께 읽어보면 좋을 논문
논문 유사도에 따라 DBpia 가 추천하는 논문입니다. 함께 보면 좋을 연관 논문을 확인해보세요!
-
A New Low Power Scan Architecture Considering Test Data Compression
대한전자공학회 ISOCC
2006 .10
-
Compression-Friendly Low Power Test Application Based on Scan Slices Reusing
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE
2016 .08
-
Low Power Scan Chain Reordering Method with Limited Routing Congestion for Code-based Test Data Compression
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE
2016 .10
-
Efficient Test Data Compression and Low Power Scan Testing in SoCs
[ETRI] ETRI Journal
2003 .10
-
A New Test Data Compression for Low Power Test
대한전자공학회 학술대회
2005 .05
-
Low power scan testing and efficient test data compression for System-On-a-Chip
ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications
2002 .07
-
Efficient Parallel Scan Test Technique for Cores on AMBA-based SoC
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE
2014 .06
-
Dynamically Changeable Secure Scan Architecture against Scan-Based Side Channel Attack
대한전자공학회 ISOCC
2012 .11
-
Segmented Scan Architecture Using Segment Grouping for Test Cost Reduction
대한전자공학회 ISOCC
2008 .11
-
Efficient Low-power Scan Test Method based on Exclusive Scan and Scan Chain Reordering
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE
2020 .08
-
System-On-a-Chip(SOC)에 대한 효율적인 테스트 데이터 압축 및 저전력 스캔 테스트
전자공학회논문지-SD
2002 .12
-
Variable-Length Block Nine-Coded Compression Technique with Huffman Codes and Symbol Merging
대한전자공학회 ISOCC
2008 .11
-
A Partial Scan Test Method without the Data Holding Overhead
ICVC : International Conference on VLSI and CAD
1997 .01
-
Master-Slave 기법을 적용한 System Operation의 동작 검증
전기학회논문지
2009 .01
-
A New Encoding Scheme for Data Storage Systems
ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications
1998 .01
-
Reduction of Test Data and Power in Scan Testing for Digital Circuits using the Code-based Technique
전자공학회논문지-IE
2008 .09
-
An Efficient Delay Test Method Using Boundary-Scan Architecture
ICVC : International Conference on VLSI and CAD
1993 .01
-
IEEE 1149.1 표준에 근거한 다중 클럭을 이용한 단일 캡쳐 스캔 설계에 적용되는 경계 주사 테스트 기법에 관한 연구
전기학회논문지
2007 .05
-
A Low Power Scan Design Architecture
대한전자공학회 ISOCC
2004 .10
-
테스트 비용 절감을 위한 스캔 체인 기반의 저전력 테스트 패턴 압축 기술
대한전자공학회 학술대회
2013 .07
이 논문의 저자 정보
최근 본 자료
댓글(0)
0
UCI(KEPA) : I410-ECN-0101-2013-569-001489331