A Low Power Scan Design Architecture

Insoo Kim ,  Susik Pa ,  k 외 1명

대한전자공학회 ISOCC

2004 .10

A New Test Data Compression for Low Power Test

Sunghoon Chun ,  Yongjoon Kim ,  Minjoo Lee 외 1명

대한전자공학회 학술대회

2005 .05

Efficient Test Data Compression and Low Power Scan Testing in SoCs

Jun-Mo Jung ,  Jong-Wha Chong

[ETRI] ETRI Journal

2003 .10

Low power scan testing and efficient test data compression for System-On-a-Chip

Jun Mo Jung ,  Jong-Wha Chong

ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications

2002 .07

Low Power Scan Chain Reordering Method with Limited Routing Congestion for Code-based Test Data Compression

Dooyoung Kim ,  M. Adil Ansa ,  i 외 3명

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE

2016 .10

A New Scan Slice Encoding Scheme with Flexible Code for Test Data Compression

Keun-Soo Lee ,  Hyuntae Pa ,  k 외 2명

대한전자공학회 ISOCC

2010 .11

테스트 비용 절감을 위한 스캔 체인 기반의 저전력 테스트 패턴 압축 기술

문창민 ,  김두영 ,  박성주

대한전자공학회 학술대회

2013 .07

An Efficient Delay Test Method Using Boundary-Scan Architecture

Yong Min Hu ,  Keun Jang Ryoo ,  Jac Heung Shin 외 5명

ICVC : International Conference on VLSI and CAD

1993 .01

System-On-a-Chip(SOC)에 대한 효율적인 테스트 데이터 압축 및 저전력 스캔 테스트

정준모 ,  정정화

전자공학회논문지-SD

2002 .12

Segmented Scan Architecture Using Segment Grouping for Test Cost Reduction

Myung-Hoon Yang ,  Taejin Kim ,  Yongjoon Kim 외 1명

대한전자공학회 ISOCC

2008 .11

Dynamically Changeable Secure Scan Architecture against Scan-Based Side Channel Attack

Yuta Atobe ,  Youhua Shi ,  Masao Yanagisawa 외 1명

대한전자공학회 ISOCC

2012 .11

A Low Power Mixed Mode Motion Estimation for Data Compression

Seongmo Pa ,  k ,  Kyoungseon Shin 외 4명

대한전자공학회 기타 간행물

2001 .11

Efficient Low-power Scan Test Method based on Exclusive Scan and Scan Chain Reordering

Dooyoung Kim ,  Jinuk Kim ,  Muhammad Ibtesam 외 4명

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE

2020 .08

Scan Cell Grouping Algorithm for Low Power Design

Insoo Kim ,  Hyoung Bok Min

Journal of Electrical Engineering & Technology

2008 .03

Are You O.K! Architecture?

조충기

건축사

2007 .01

저전력을 고려한 스캔 체인 구조 변경

金吝洙 ,  閔炯福

전기학회논문지 D

2005 .07

A Novel High Performance Scan Architecture with Dmuxed Scan Flip-Flop (DSF) for Low Shift Power Scan Testing

Jung-Tae Kim ,  Insoo Kim ,  Keon-Ho Lee 외 4명

Journal of Electrical Engineering & Technology

2009 .12

Compression-Friendly Low Power Test Application Based on Scan Slices Reusing

Wang Weizheng ,  Wang JinCheng ,  Cai Shuo 외 2명

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE

2016 .08

Master-Slave 기법을 적용한 System Operation의 동작 검증

金吝洙 ,  閔炯福

전기학회논문지

2009 .01