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논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 대한전기학회 Journal of Electrical Engineering & Technology Journal of Electrical Engineering & Technology Vol.4 No.4
- 발행연도
- 2009.12
- 수록면
- 559 - 565 (7page)
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초록· 키워드
오류제보하기
Power dissipation during scan testing is becoming an important concern as design sizes and gate densities increase. The high switching activity of combinational circuits is an unnecessary operation in scan shift mode. In this paper, we present a novel architecture to reduce test power dissipation in combinational logic by blocking signal transitions at the logic inputs during scan shifting. We propose a unique architecture that uses dmuxed scan flip-flop (DSF) and transmission gate as an alternative to muxed scan flip-flop. The proposed method does not have problems with auto test pattern generation (ATPG) techniques such as test application time and computational complexity. Moreover, our elegant method improves performance degradation and large overhead in terms of area with blocking logic techniques. Experimental results on ITC99 benchmarks show that the proposed architecture can achieve an average improvement of 30.31% in switching activity compared to conventional scan methods. Additionally, the results of simulation with DSF indicate that the powerdelay product (PDP) and area overhead are improved by 28.9% and 15.6%, respectively, compared to existing blocking logic method.
목차
Abstract
1. Introduction
2. Previous work
3. Proposed Scan Architecture for Reducing Shift Power Dissipitation
4. Experimental and Simulation Results
5. Conclusion
Acknowledgements
References
참고문헌 (19)
참고문헌 신청
1. [단행본] - Laung-Terng Wang / 2006 / VLSI Test Principles and Architecture,Design For Testability / Elsevier Inc
2. [학술지(정기간행물)] - Patrick Girad / 2002 / Survey of Low-Power Testing of VLSI Circuits / IEEE Design & Test of Computers 19 (3) : 82 ~ 92
3. [학술지(정기간행물)] - Insoo Kim / 2008 / Scan Cell Grouping Algorithm for Low Power Design / Journal of Electrical Engineering & Technology 3 (1) : 130 ~ 134
4. [학술대회논문] - Xiaoqing Wen / 2005 / On Low-Capture-Power Test Generation for Scan Testing / Proceedings of the 23rd IEEE VLSI Test Symposium (VTS’05)
5. [학술대회논문] - Elif Alpaslan / 2008 / Reducing Scan Shift Power at RTL / IEEE VLSI Test Symposium : 139 ~ 146
2. [학술지(정기간행물)] - Patrick Girad / 2002 / Survey of Low-Power Testing of VLSI Circuits / IEEE Design & Test of Computers 19 (3) : 82 ~ 92
3. [학술지(정기간행물)] - Insoo Kim / 2008 / Scan Cell Grouping Algorithm for Low Power Design / Journal of Electrical Engineering & Technology 3 (1) : 130 ~ 134
4. [학술대회논문] - Xiaoqing Wen / 2005 / On Low-Capture-Power Test Generation for Scan Testing / Proceedings of the 23rd IEEE VLSI Test Symposium (VTS’05)
5. [학술대회논문] - Elif Alpaslan / 2008 / Reducing Scan Shift Power at RTL / IEEE VLSI Test Symposium : 139 ~ 146
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