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학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
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논문 기본 정보
- 자료유형
- 학술대회자료
- 저자정보
- 발행연도
- 2009.11
- 수록면
- 492 - 495 (4page)
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초록· 키워드
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As the semiconductor process advances below 90nm technology node, leakage power has been an ever more serious concern. One of the most effective ways of reducing leakage power is power gating the circuits. Our work tries to find a microarchitectural way of applying power gating technique to functional units in a processor, while avoiding processor stalls, separate power control instructions, and much hardware overhead. We focus on loops, which typically cause long idle period for some functional units that are not used in the loops. Assuming that the target processor has zero-overhead loop feature, we exploit the existing hardware loop counter to determine when to wake up the functional units that have been turned off with the start of the loop execution. We use our own processor, ODALRISC, synthesized with 45nm process library and a C compiler to execute several benchmarks and realistic applications and obtain power report. The experimental results show that our approach achieves about 30% leakage power reduction on average in functional units for JPEG applications, with no performance degradation.
목차
Abstract
I. INTRODUCTION
II. RELATED WORKS
III. MOTIVATIONAL EXAMPLE
IV. TARGET PROCESSOR ARTHICTECTURE
V. COMPILE-TIME POWER CONTROL DECISIONS
VI. EXPERIMENTS
VII. CONCLUSIONS
ACKNOWLEDGEMENT
REFERENCES
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UCI(KEPA) : I410-ECN-0101-2013-569-001483324