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논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE Journal of Semiconductor Technology and Science Vol.17 No.1
- 발행연도
- 2017.2
- 수록면
- 156 - 161 (6page)
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이 논문의 연구 히스토리 (2)
2017
Investigation of Junction-less Tunneling Field Effect Transistor (JL-TFET) with Floating Gate
Asif Ali
,
Dongsun Seo
,
Il Hwan Cho
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE
2017.02
학술저널
Investigation of Junction-less Tunneling Field Effect Transistor with Floating Gate
Asif Ali
일반
2017.01
학위논문
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초록· 키워드
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This work presents a novel structure for junction-less tunneling field effect transistor (JLTFET) with a floating gate over the source region. Introduction of floating gate instead of fixed metal gate removes the limitation of fabrication process suitability. The proposed device is based on a heavily n-type-doped Si-channel junction-less field effect transistor (JLFET). A floating gate over source region and a control-gate with optimized metal workfunction over channel region is used to make device work like a tunnel field effect transistor (TFET). The proposed device has exhibited excellent ID-VGS characteristics, ION/IOFF ratio, a point subthreshold slope (SS), and average SS for optimized device parameters. Electron charge stored in floating gate, isolation oxide layer and body doping concentration are optimized. The proposed JL-TFET can be a promising candidate for switching performances.
목차
Abstract
Ⅰ. INTRODUCTION
Ⅱ. DEVICE STRUCTURE AND OPERATION
Ⅲ. RESULTS AND DISCUSSIONS
Ⅳ. CONCLUSIONS
REFERENCES
참고문헌 (14)
참고문헌 신청
T. Skotnicki, et al, “The end of CMOS scaling: toward the introduction of new materials and structural changes to improve MOSFET performance,” Circuits and Devices, IEEE Magazine of, Vol.21, No.1, pp.16-26, Feb.,2005.
R. R. Troutman, “VLSI limitations from draininduced barrier lowering,” Solid-State Circuits, IEEE Journal of, Vol.14, NO.2, pp.383-391, Apr., 1979.
G. V. William, et al, “Figure of merit for and identification of sub-60 mV/decade devices,” Applied Physics Lett., Vol.102, No.1, pp.013510(1- 4), Jan., 2013
L. Chang, et al, “Direct-tunneling gate leakage current in double-gate and ultrathin body MOSFETs,” Electron Devices, IEEE Transactions on, Vol.49, No.12, pp.2288-2295, Dec., 2002.
K. Boucart and A. M. Ionescu, “Double-gate tunnel FET with High-κ gate dielectric,” Electron Devices, IEEE Transactions on, Vol.54, No.7, pp.1725-1733, Jun., 2007.
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UCI(KEPA) : I410-ECN-0101-2017-569-002321612