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논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE Journal of Semiconductor Technology and Science Vol.21 No.2
- 발행연도
- 2021.4
- 수록면
- 92 - 100 (9page)
- DOI
- 10.5573/JSTS.2021.21.2.092
이용수
초록· 키워드
오류제보하기
In this paper, it is shown that the erase efficiency of the Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) type nonvolatile charge trapping memory (CTM) is greatly improved by adjusting boron doping. Tunnel FET (TFET) based SONOS memory, which has p-type at source side, is superior to MOSFET based SONOS memory in terms of hole supplement and erase speed. In order to discover the specific physical reasons of this erase speed enhancement, MOSFET based SONOS memory devices with different body doping concentration are additionally investigated. As a result, it is found that the more hole supplement from source side in TFET and body side in MOSFET accelerates the erase speed and erase speed enhancement can be realized by utilizing boron doping. Furthermore, erase speed depending on device geometry, in terms of source-to-gate overlap length and gate length, is also analyzed. Interestingly, it is demonstrated that source overlap technique, which has been implemented for suppression of ambipolar current, is also possible to accelerate erase speed.
목차
Abstract
I. INTRODUCTION
II. DEVICE STRUCTURE AND MODEL PHYSICS
III. DEMONSTRATION OF ERASE SPEED ENHANCEMENT
IV. ADDITIONAL PHYSICAL ANALYZATION ON ERASE SPEED ENHANCEMENT
V. CONCLUSIONS
REFERENCES
참고문헌 (33)
참고문헌 신청
Y. Liu, et al., "Electric Field Induced Nitride Trapped Charge Lateral Migration in a SONOS Flash Memory," IEEE Electron Device Letters, Vol. 38, No. 1, pp. 48-51, Jan. 2017.
E. R. Hsieh, H. T. Wang, S. S. Chung, W. Chang, S. D. Wang and C. H. Chen, "Experimental techniques on the understanding of the charge loss in a SONOS nitride-storage nonvolatile memory," 2016 IEEE 23rd International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA), pp. 38-42, July 2016.
D. Gupta and S. K. Vishvakarma, "Impact of LDD Depth Variations on the Performance Characteristics of SONOS NAND Flash Device," IEEE Transactions on Device and Materials Reliability, Vol. 16, No. 3, pp. 298-303, Sep. 2016.
J. -W. Jung and W. -J. Cho, “Tunnel Barrier Engineering for Non-Volatile Memory,” Journal of Semiconductor Technology and Science, Vol. 8, No. 1, pp. 32-39, Mar. 2008.
T. Kim, K. Park, T. Jang, M. H. Baek, Y. S. Song and B. -G. Park, “Input-modulating adaptive neuron circuit employing asymmetric floating-gate MOSFET with two independent control gates,” Solid-State Electronics, Vol. 163, pp. 107667-1-107667-5, Jan. 2020.
E. R. Hsieh, H. T. Wang, S. S. Chung, W. Chang, S. D. Wang and C. H. Chen, "Experimental techniques on the understanding of the charge loss in a SONOS nitride-storage nonvolatile memory," 2016 IEEE 23rd International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA), pp. 38-42, July 2016.
D. Gupta and S. K. Vishvakarma, "Impact of LDD Depth Variations on the Performance Characteristics of SONOS NAND Flash Device," IEEE Transactions on Device and Materials Reliability, Vol. 16, No. 3, pp. 298-303, Sep. 2016.
J. -W. Jung and W. -J. Cho, “Tunnel Barrier Engineering for Non-Volatile Memory,” Journal of Semiconductor Technology and Science, Vol. 8, No. 1, pp. 32-39, Mar. 2008.
T. Kim, K. Park, T. Jang, M. H. Baek, Y. S. Song and B. -G. Park, “Input-modulating adaptive neuron circuit employing asymmetric floating-gate MOSFET with two independent control gates,” Solid-State Electronics, Vol. 163, pp. 107667-1-107667-5, Jan. 2020.
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