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논문 기본 정보
- 자료유형
- 학술대회자료
- 저자정보
- 발행연도
- 2023.6
- 수록면
- 320 - 324 (5page)
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초록· 키워드
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This paper presents a novel design for the heterogate Tunnel Field-Effect Transistor (TFET) with a pocket region to enhance its on current performance. The proposed design optimizes the length ratio of high-k dielectric material and SiO₂ and carefully selects the location of the pocket in consideration of the low doped region between the source and the pocket. Through two optimization processes, the off current is maintained while the on current is improved in the proposed TFET structure. The performance of the proposed design is analyzed using TCAD simulation, which shows a significant improvement in the on current. This design has the potential to be an attractive candidate for low-power and high-performance applications.
목차
Abstract
Ⅰ. 서론
Ⅱ. 본론
Ⅳ. 결론 및 향후 연구 방향
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