지원사업
학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
커뮤니티
연구자들이 자신의 연구와 전문성을 널리 알리고, 새로운 협력의 기회를 만들 수 있는 네트워킹 공간이에요.
초록· 키워드
오류제보하기
In this study, we have fabricated and characterized vertical double-gate (DG) InGaAs tunnel field-effect-transistors (TFETs) with Al2O3/HfO2 = 1/5 nm bi-layer gate dielectric by employing a top-down approach. The device exhibited excellent characteristics including a minimum subthreshold swing of 60 mV/decade, a maximum transconductance of 141 μS/μm, and an on/off current ratio of over 103 at 20o C. Although the TFETs were fabricated using a dry etch-based top-down approach, the values of DIBL and hysteresis were as low as 40 mV/V and below 10 mV, respectively. By evaluating the effects of constant voltage and hot carrier injection stress on the vertical DG InGaAs TFET, we have identified the dominant charge trapping mechanism in TFETs.
목차
등록된 정보가 없습니다.
참고문헌 (0)
참고문헌 신청함께 읽어보면 좋을 논문
논문 유사도에 따라 DBpia 가 추천하는 논문입니다. 함께 보면 좋을 연관 논문을 확인해보세요!
-
터널링 전계효과 트랜지스터 4종류 특성 비교
한국정보통신학회논문지
2017 .05
-
동종 접합 InGaAs 수직형 Fin TFET의 온도 의존 DC 특성에 대한 연구
센서학회지
2020 .01
-
A Vertical Gate-Source Overlapped TFET (Tunneling Field effect Transistor) for Ultra Low Power Application
ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications
2015 .06
-
Effects of Pillar Conditions on DC/AC Characteristics of Tunnel Field-effect Transistor with Vertical Structures
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE
2021 .08
-
General SPICE Modeling Procedure for Double-Gate Tunnel Field-Effect Transistors
Journal of information and communication convergence engineering
2016 .06
-
Investigation of Feasibility of Tunneling Field Effect Transistor (TFET) as Highly Sensitive and Multi-sensing Biosensors
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE
2017 .02
-
시뮬레이션을 통한 TFET 소자에서의 Source-to-Gate Underlap/Overlap 길이에 따른 특성 변화 연구
대한전자공학회 학술대회
2016 .11
-
Triple-gate Tunnel FETs Encapsulated with an Epitaxial Layer for High Current Drivability
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE
2017 .04
-
Switching Performance Investigation of a Gate-All-Around Core-Source InGaAs/InP TFET
Transactions on Electrical and Electronic Materials
2021 .08
-
Characteristics and optimization of reverse structured two source region tunnel TFET
대한전자공학회 학술대회
2019 .06
-
Capacitance model of Single-Gate Tunneling Field-Effect Transistors for Circuit Simulation
INTERNATIONAL CONFERENCE ON FUTURE INFORMATION & COMMUNICATION ENGINEERING
2017 .06
-
Si, Ge과 Si-Ge Hetero 터널 트랜지스터의 라인 터널링과 포인트 터널링에 대한 연구
한국정보통신학회논문지
2017 .05
-
Compact Capacitance Model of L-Shaped Tunneling Field-effect Transistors
INTERNATIONAL CONFERENCE ON FUTURE INFORMATION & COMMUNICATION ENGINEERING
2021 .02
-
개선된 성능을 위해 포켓이 추가된 Hetero-gate TFET 구조
대한전자공학회 학술대회
2023 .06
-
Compact Current Model of Single-Gate/Double-Gate Tunneling Field-Effect Transistors
Journal of Electrical Engineering & Technology
2017 .09
-
A Recessed-channel Tunnel Field-Effect Transistor (RTFET) with the Asymmetric Source and Drain
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE
2016 .10
-
Design Optimization of L-Shaped Gate Negative Capacitance Si/Ge Heterojunction TFET With Channel Doping
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE
2025 .02
-
Doping-less Tunnel Field-effect Transistor with a Gate Insulator Stack to Adjust Tunnel Barrier
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE
2022 .04
-
터널링 전계효과 트랜지스터로 구성된 3차원 적층형 집적회로에 대한 연구
한국정보통신학회논문지
2022 .05
-
TFET 기반 gate-all-around(GAA) SONOS 메모리의 프로그램 성능 향상
대한전자공학회 학술대회
2022 .06
이 논문의 저자 정보
최근 본 자료
댓글(0)
0