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논문 기본 정보
- 자료유형
- 학술대회자료
- 저자정보
- 발행연도
- 2024.6
- 수록면
- 826 - 829 (4page)
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초록· 키워드
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In this study, a complementary tunnel field-effect transistor (CTFET) is proposed and its electrical characteristics are examined by using a three-dimensional technology computer-aided design (TCAD) simulation. The proposed CTFET features monolithically stacked n- and p-channel TFETs for the better integration density as well as low power consumption. The operation mechanisms and transfer curves of n- and p-channel TFETs are analyzed, herein. Both TFETs show high on-off current ratio (~107), low-level off-state current (6 ×10-16 A/μm) and symmetric transfer curves which allows low-power CMOS operation.
목차
Abstract
Ⅰ. 서론
Ⅱ. 본론
Ⅲ. 시뮬레이션 결과
Ⅳ. 결론 및 향후 연구 방향
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