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논문 기본 정보
- 자료유형
- 학술대회자료
- 저자정보
- 저널정보
- 대한전자공학회 ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications ITC-CSCC : 2009
- 발행연도
- 2009.7
- 수록면
- 420 - 423 (4page)
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초록· 키워드
오류제보하기
As the miniaturization of manufacturing process gets advanced, leakage power consumption quickly increases and becomes dominant in the total power consumption. Power Gating (PG) is a well-known technique that efficiently reduces leakage power. However effectiveness by applying PG to Functional units of a Superscalar processor has not been studied enough. In this paper, we investigated the effectiveness for a Superscalar processor assuming “2Way” and “4Way” by using a Simplescalar processor simulator with “pisa” architecture. Simulation results for programs in SPEC CPU 2000 and MiBench showed that applying PG to one ALU in four integer ALUs is effective in “4Way.” Effective sleep cycles that gives the net energy-savings occupy 63% in the total execution cycles on average. Applying PG to the integer Mult/Div also contributes to energy reduction. In “2Way,” only applying PG to the integer Mult/Div is effective.
목차
Abstruct
1. Introduction
2. PG for Functional units of a Superscalar processor
3. Evaluation method
4. Results
5. Conclusion
References
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UCI(KEPA) : I410-ECN-0101-2012-569-004020725